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1 2 - bit, 1 gsps /500 msps jesd204b, dual analog - to - digital converter data sheet ad9234 features jesd204b (s ubclass 1) coded serial digital outputs 1.5 w total power per channel at 1 gsps (default s ettings) sfdr 79 db fs at 34 0 mhz (1 gsps) 86 dbfs at 340 mhz (500 msps) snr 6 3.4 dbfs at 340 mhz (a in = ?1.0 dbfs , 1 gsps ) 65.6 dbfs at 340 mhz (a in = ?1.0 dbfs, 500 msps) enob = 10. 4 bits at 10 mhz dnl = 0.16 lsb ; inl = 0.35 lsb noise d ensity ? 151 dbfs/hz ( 1 gsps ) ? 150 dbfs/hz ( 500 msps ) 1.2 5 v , 2.5 v , and 3.3 v dc supply operation low swing full scale input 1.34 v p - p nominal (1 gsps) 1.63 v p - p nominal (500 msps) no missing codes internal adc voltage reference flexible termination i mpedance 400 , 200 , 100 , and 5 0 differential 2 ghz usable analog input full power bandwidth 95 db channel isolation/crosstalk amplitude detect bits for eff icient agc implementation differential clock input optional decimate - by - 2 ddc per channel differential clock i nput integer clock divide by 1, 2 , 4 , or 8 flexible jesd204b lane c onfigurations small signal d ither applications communications diversity multi band, multi mode digital receivers 3g/4g, td - scdma, w - cdma, gsm, lte point - to - point r adio systems digital predistortion observation path general - purpose software radios ultrawideband satellite r eceiver instrumentation (spectrum analyzers, network analyzers, integrated rf test solutions ) digital oscilloscopes high speed data acquisition systems docsis 3.0 cmts upstream receive paths hfc digital reverse path receivers func tional block diagram figure 1. product highlights 1. lo w power consumption analog core, 12 - bit, 1.0 gsps dual analog - to - digit al converter ( adc ) with 1. 5 w per channel. 2. wide full power b andwidth support s if sampling of signals up to 2 ghz. 3. buffered i nputs with programmable input termination eases filter design and implementation. 4. flexible serial port interface (spi) controls various product features and functions to meet specifi c system requirements. 5. programmable f ast o ver r ange detec t ion . 6. 9 mm 9 mm 64 - l ead lfcsp . 7. pin compatible with the ad9680 1 4 - bit , 1 gsps/ 500 msps d ual adc. vin+a vin?a vin+b vin?b clk+ clk? ad9234 serdout0 serdout1 serdout2 serdout3 2 4 sysref clock generation and adjust 12 12 pdwn/ stby syncinb fd_a fd_b buffer buffer jesd204b high speed serializer + tx outputs jesd204b subclass 1 control v_1p0 8 fast detect agnd drgnd dgnd sdio sclk csb avdd1 (1.25v) avdd2 (2.5v) avdd3 (3.3v) avdd1_sr (1.25v) dvdd (1.25v) drvdd (1.25v) spivdd (1.8v to 3.3v) 4 fast detect signal monitor adc core adc core spi control decimate by 2 decimate by 2 signal monitor 12244-001 rev. a document feedback inform ation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specificatio ns subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ad9234 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 general description ......................................................................... 4 specificat ions ..................................................................................... 5 dc specifications ......................................................................... 5 ac specifications .......................................................................... 6 digital specifications ................................................................... 8 switching specifications .............................................................. 9 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configuratio n and function descriptions ........................... 12 typical performance characteristics ........................................... 14 ad9234 - 1000 .............................................................................. 14 ad9234 - 500 ................................................................................ 18 equivalent circuit s ......................................................................... 22 theory of operation ...................................................................... 24 adc architecture ...................................................................... 24 analog input considerations .................................................... 24 voltage reference ....................................................................... 27 clock input considerations ...................................................... 28 power - down/standby mode .................................................... 29 temperature diode .................................................................... 29 adc overra nge and fast detect .................................................. 30 adc overrange .......................................................................... 30 fast threshold detection (fd_a and fd_b) ........................ 30 signal monitor ................................................................................ 31 digital downco nverter (ddc) ..................................................... 34 ddc general description ........................................................ 34 half - band filter .......................................................................... 35 ddc gain stage ......................................................................... 36 ddc complex to real conversion ......................................... 36 digital outputs ............................................................................... 37 introduction to the jesd204b interface ................................. 37 jesd204b overview .................................................................. 37 functional overview ................................................................. 38 jesd204b link establishment ................................................. 39 physical layer (driver) outputs .............................................. 41 configuring the jesd204b link .............................................. 43 multichip synchronization ............................................................ 46 sysref setup/hold window monitor ................................. 48 test modes ....................................................................................... 50 adc test modes ........................................................................ 50 jesd204b block test modes .................................................... 51 serial port interface ........................................................................ 53 configuration using the spi ..................................................... 53 hardware interface ..................................................................... 53 spi access ible features .............................................................. 53 memory map .................................................................................. 54 reading the memory map register table ............................... 54 memory map register table ..................................................... 55 applications information .............................................................. 65 powe r supply recommendations ............................................. 65 exposed pad thermal heat slug recommendations ............ 65 avdd1_sr (pin 57) and agnd (pin 56 and pin 60) .............. 65 outline dimensions ....................................................................... 66 ordering guide .......................................................................... 66 rev. a | page 2 of 66
data sheet ad9234 rev. a | page 3 of 66 revision history 3/15rev. 0 to rev. a added ad9234-500 ........................................................... universal changes to features section ............................................................ 1 changes to table 1 ............................................................................ 5 changes to table 2 ............................................................................ 6 changes to table 4 ............................................................................ 9 changes to table 6, thermal characteristics section, and table 7 ............................................................................................... 11 added ad9234-500 section and figure 29 to figure 51 ........... 18 changes to figure 63 and figure 64 captions, analog input controls and sfdr optimization section, and figure 66 ........ 25 changes to figure 70 and figure 71 ............................................... 26 changes to voltage referece section .............................................. 27 changes to figure 79 ...................................................................... 28 changes to figure 80 ...................................................................... 29 changes to figure 91 ...................................................................... 38 changes to ddc general description section .......................... 34 added example 2: full bandwidth mode at 500 msps section... 44 added test modes section and table 15 to table 19 ................. 50 changes to table 22 ........................................................................ 55 changes to power supply recommendations section and figure 106 ......................................................................................... 65 changes to ordering guide ........................................................... 66 8/14revision 0: initial version
ad9234 data sheet general description the ad 9234 is a dual, 12 - bit , 1 gsps /500 msps adc. the device h as an on - chip buffer and sample - and - hold circuit designed for low power, small size , and ease of use. this product is designed for sampling wide bandwidth analog signals. the ad9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity , and low power in a small package. the dual adc cores feature a multistage, differential pipelined architecture with integrated output err or correction logic. each adc features wide bandwidth buffered inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. each adc data output is internally co nnected to an optional d ecimate - by - 2 block. the ad9234 has several functions that simplify the automatic gain control (agc) function in a communications receiver. the programmable threshold detector allows monitoring of the incom ing signal power using the fast detect output bits of the adc. if the input signal level exceeds the programmable threshold, the fast detect indicator goes high. because this threshold indicator has low latency, the user can quickly turn down the system ga in to avoid an overrange condition at the adc input. in addition to the fast detect outputs, the ad9234 also offer s signal monitoring capability. the signal monitoring block provides additional information about the signal being digitized by the adc. users can configure the subclass 1 jesd204b - base d high speed ser ialized output in a variety of one - , two - , o r four - lane configurations, depending on t he acceptable lane rate of the receiving logic device and the sampling rate of the adc. multiple device synchronization is supported through the sysref and syncinb input pins. the ad9234 has fle xible power - down options that allow significant power savings when desired. all of these features can be programmed using a 1.8 v to 3.3 v capable 3 - wire spi. the ad9234 is available in a pb - free , 64 - lead l fcsp and is specified over the ? 40c to +85c industrial temperature range. this product is protected by a u .s . patent. rev. a | page 4 of 66
data sheet ad9234 specifications dc specifications avdd1 = 1.2 5 v, av d d 2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.2 5 v, dvdd = 1.2 5 v, drvdd = 1.2 5 v, s p i v d d = 1.8 v , spec ified maximum sampling rate , a in = ?1.0 dbfs, clock divider = 2 , default spi settings, t a = 25c, u nless otherwise noted. table 1. ad9234 - 500 ad9234 - 1000 parameter temp min typ max min typ max unit resolution full 12 12 bits accuracy no missing codes full guaranteed guaranteed offset error full ? 0.22 0 +0.20 ? 0.22 0 +0.20 % fsr offset matching full 0 +0.19 0 +0.19 % fsr gain error full ? 13.8 ? 5.1 +3.6 0 % fsr gain matching full ? 3.9 +1 +5.9 1 +4.8 % fsr differential nonlinearity (dnl) full ? 0.3 +0.3 ? 0.3 0.16 +0.3 lsb integral nonl inearity (inl) full ? 0.8 +1.1 ? 1.2 35 +1.4 lsb temperature drift offset error 25c 2.6 6 ppm/
ad9234 data sheet ad9234 - 500 ad9234 - 1000 parameter temp min typ max min typ max unit power consumption total power dissipation (including output drivers) 2 full 2.15 2.5 3.0 3.3 w total power dissipation ( l = 2 mode ) 25c 2.08 n/a 3 w power - down dissipation full 670 750 mw standby 4 full 1.1 1.25 w 1 all lanes running. power dissipation on drvdd changes with lane rate and number of lanes used. 2 default mode. no ddcs used. l = 4, m = 2, f = 1. 3 n/a = not applicable. at the maximum sample rate, it is not applicable to use l = 2 mode on the jesd204b output interface because this exceeds the maximum lane rate of 12.5 gbps. l = 2 mode is supported when the equation ((m n? (10/8) f out )/l) results in a line rate that is 12.5 gbps. f out is the output sample rate and is denoted by f s /dcm, where dcm = decimation ratio. 4 can be controlled by the spi. ac specifications avdd1 = 1.25 v, av d d 2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, spec ified maximum sampling rate, a in = ? 1.0 dbfs, clock divider = 2 , default spi settings, t a = 25c, unless otherwise noted. table 2 . ad9234 - 500 ad9234 - 1000 parameter 1 temp min typ max min typ max unit analog input full scale full 1.63 1.3 4 v p -p noise density 2 full ? 150 ? 151 dbfs/hz signal -to - noise ratio (snr) 3 f in = 10 mhz 25c 65.9 64.2 dbfs f in = 170 mhz full 65.1 65.8 61.6 63.9 dbfs f in = 340 mhz 25c 65.6 63.4 dbfs f in = 450 mhz 25c 65. 3 63.1 dbfs f in = 7 37 mhz 25c 64.2 61.6 dbfs f in = 985 mhz 25c 63.6 60.7 dbfs f in = 1410 mhz 25c 62.2 58.8 dbfs snr and distortion ratio (sinad) 3 f in = 10 mhz 25c 65.8 64.1 dbfs f in = 170 mhz full 65.0 65.7 61.2 63.8 dbfs f in = 340 mhz 25c 65.5 63.3 dbfs f in = 450 mhz 25c 65.2 63.0 dbfs f in = 737 mhz 25c 63.7 61.5 dbfs f in = 985 mhz 25c 63.1 60.6 dbfs f in = 1410 mhz 25c 61.2 58.7 dbfs effective number of bits (enob) f in = 10 mhz 25c 10.7 10.4 bits f in = 170 mhz full 10.5 10.6 9.9 10.3 bits f in = 340 mhz 25c 10.6 10.2 bits f in = 450 mhz 25c 10.5 10.2 bits f in = 737 mhz 25c 10.3 9.9 bits f in = 985 mhz 25c 10.2 9.8 bits f in = 1410 mhz 25c 9.9 9.5 bits spurious - free dynamic range (sfdr) 3 f in = 10 mhz 25c 84 89 dbfs f in = 170 mhz full 77 85 70 80 dbfs f in = 340 mhz 25c 85 79 dbfs f in = 450 mhz 25c 87 80 dbfs f in = 737 mhz 25c 75 81 dbfs f in = 985 mhz 25c 75 79 dbfs f in = 1410 mhz 25c 71 78 dbfs rev. a | page 6 of 66
data sheet ad9234 ad9234 - 500 ad9234 - 1000 parameter 1 temp min typ max min typ max unit worst harmonic, second or third 3 f in = 10 mhz 25c ? 84 ? 89 dbfs f in = 170 mhz full ? 85 ? 77 ? 80 ? 70 dbfs f in = 340 mhz 25c ? 85 ? 79 dbfs f in = 450 mhz 25c ? 87 ? 80 dbfs f in = 737 mhz 25c ? 75 ? 82 dbfs f in = 985 mhz 25c ? 75 ? 79 dbfs f in = 1410 mhz 25c ? 71 ? 78 dbfs worst other, excluding second or third harmonic 3 f in = 10 mhz 25c ? 96 ? 89 dbfs f in = 170 mhz full ? 82 ? 95 ? 85 ? 76 dbfs f in = 340 mhz 25c ? 94 ? 83 dbfs f in = 450 mhz 25c ? 93 ? 82 dbfs f in = 737 mhz 25c ? 88 ? 81 dbfs f in = 985 mhz 25c ? 89 ? 85 dbfs f in = 1410 mhz 25c ? 86 ? 80 dbfs two - tone intermodulation distortion (imd), a in1 and a in2 = ?7 dbfs f in1 = 18 7 mhz, f in2 = 1 90 mhz 25c ? 90 ? 81 dbfs f in1 = 338 mhz, f in2 = 341 mhz 25c ? 86 ? 78 dbfs crosstalk 4 25c 95 95 db full power bandwidth 5 25c 2 2 ghz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 noise density is measured at a low analog input frequency (30 mhz). 3 see table 9 for recommended settings for the buffer current setting optimized for sfdr. 4 crosstalk is measured at 170 mhz with a ?1.0 dbfs analog input on one channel and no input on the adjacent channe l. 5 measured with circuit shown in figure 64 . rev. a | page 7 of 66
ad9234 data sheet digital specificatio ns avdd1 = 1.25 v, av d d 2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, spec ified maximum sampling rate, a in = ? 1.0 dbfs, default spi settings, t a = 25c, unless otherwise noted. table 3 . parameter temperature min typ max unit clock inputs (clk+, clk ?) logic compliance full lvds/lvpecl differential input voltage full 600 1200 1800 mv p -p input common - mode voltage full 0.85 v input resistance (differential) full 35 k input capacitance full 2.5 pf system reference inputs (sysref+, sysref?) logic compliance full lvds/lvpecl differential input voltage full 40 0 1200 1800 mv p -p input common - mode voltage full 0.6 0.85 2.0 v input resistance (differential) full 35 k input capacitance (differential) full 2.5 pf logic inputs (sdi o , sclk, csb , pdwn/stby) logic compliance full cmos logic 1 voltage full 0.8 spivdd v logic 0 voltage full 0 0.5 v input resistance full 30 k logic output (sdio) logic compliance full cmos logic 1 voltage (i oh = 800 a) full 0.8 spivdd v logic 0 voltage (i ol = 50 a) full 0 0.5 v sync inputs (syncinb+, syncinb?) logic compliance full lvds/lvpecl/cmos differential input voltage full 400 1200 1800 mv p -p input common - mode voltage full 0.6 0.85 2.0 v input resistance (differential) full 35 k input capacitance full 2.5 pf logic outputs (fd_a, fd_b) logic compliance full cmos logic 1 voltage full 0.8 spivdd v logic 0 voltage full 0 0.5 v input resistance full 30 k digital outputs (serdoutx, x = 0 to 3) logic compliance full cml differential output voltage full 360 770 mv p -p output common - mode voltage (v cm ) ac - coupled 25c 0 1.8 v short - circuit current (i dshort ) 25c ? 100 +100 ma differential return loss (rl diff ) 1 25c 8 db common - mode return loss (rl cm ) 1 25c 6 db differential termination impedance full 80 100 120 1 differential and common - mode return loss is measured from 100 mhz to 0.75 mhz baud rate. rev. a | page 8 of 66
data sheet ad9234 switching specifications avdd1 = 1.25 v, av dd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, spec ified maximum sampling rate, a in = ? 1.0 dbfs, default spi settings, t a = 25c, unless otherwise noted. table 4 . ad9234 - 500 ad9234 - 1000 parameter temperature min typ max min typ max unit clock clock rate (at clk+/clk? pins) full 0.3 4 0.3 4 ghz maximum sample rate 1 full 5 00 1000 msps min imum sample rate 2 full 300 300 msps clock pulse width high full 1000 500 ps clo ck pulse width low full 1000 500 ps output parameters unit interval (ui) 3 full 80 2 00 80 100 ps rise time (t r ) (20% to 80% into 100 load) 25c 24 32 24 32 ps fall time (t f ) (20% to 80% into 100 load) 25c 24 32 24 32 ps pll lock time 25c 2 2 ms data rate per channel (nrz) 4 25c 3.125 5 12.5 3.125 10 12.5 gbps latency 5 pipeline latency full 55 55 cl oc k cycles fas t detect latency full 28 28 cl oc k cycles wak e - up time 6 sta ndby 25c 1 1 m s power - down 25c 4 4 m s aperture aperture delay (t a ) full 530 530 p s ape rture uncertainty (jitter, t j ) full 55 55 fs rms out - of - range recovery time full 1 1 cl oc k cycles 1 the maxim um sample rate is the clock rate after the divider. 2 the minimum sample rate operates at 300 msps with l = 2 or l = 1. 3 baud rate = 1/ui. a subset of this range can be supported . 4 default l = 4. this number can be changed based on the sample rate and de cimation ratio. 5 no ddcs used. l = 4, m = 2, f = 1. 6 wake - up time is defined as the time required to return to normal operation from power - down mode. timing specification s table 5 . parameter test conditions/comments min typ max unit clk + to sysref + timing requirements see figure 2 t su_sr device clock to sysref + setup time 117 p s t h_sr device clock to sysref + hold time ? 96 p s spi timing requirements see figure 3 t ds setup time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk must be in a logic high state 10 ns t low minimum period that sclk must be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 3 ) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 3 ) 10 ns rev. a | page 9 of 66
ad9234 data sheet rev. a | page 10 of 66 timing diagrams figure 2. sysref setup and hold timing figure 3. serial port interface timing diagram figure 4. data output timing (full bandwidth mode; l = 4; m = 2; f = 1) clk+ clk? sysref+ sysref? t su_sr t h_sr 12244-003 don?t care don?t care don?t care don?t care sdio sclk t s t dh t clk t ds t access t h r/w a14a13a12a11a10a9a8a7 d5d4d3d2d1d0 t low t high csb 12244-004 serdout0? n ? 54 n ? 53 n ? 52 n ? 51 n ? 1 sample n n + 1 aperture delay n ? 55 clk+ clk? clk+ clk? serdout0+ serdout1? serdout1+ serdout2? serdout2+ serdout3? serdout3+ abcdefgh i jabcdefgh i jabcdefgh i j abcdefgh i jabcdefgh i jabcdefgh i j abcdefgh i jabcdefgh i jabcdefgh i j abcdefgh i jabcdefgh i jabcdefgh i j converter0 msb converter0 lsb converter1 msb converter1 lsb analog input signal sample n ? 55 encoded into 1 8-bit/10-bit symbol sample n ? 54 encoded into 1 8-bit/10-bit symbol sample n ? 53 encoded into 1 8-bit/10-bit symbol 12244-002
data sheet ad9234 rev. a | page 11 of 66 absolute maximum ratings table 6. parameter rating electrical avdd1 to agnd 1.32 v avdd1_sr to agnd 1.32 v avdd2 to agnd 2.75 v avdd3 to agnd 3.63 v dvdd to dgnd 1.32 v drvdd to drgnd 1.32 v spivdd to agnd 3.63 v agnd to drgnd ?0.3 v to +0.3 v vinx to agnd 3.2 v sclk, sdio, csb to agnd ?0.3 v to spivdd + 0.3 v pdwn/stby to agnd ?0.3 v to spivdd + 0.3 v operating temperature range ?40c to +85c junction temperature range ?40c to +115c storage temperature range (ambient) ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characteristics typical ja , jb , and jc are specified vs. the number of printed circuit board (pcb) layers in different airflow velocities (in m/sec). airflow increases heat dissipation effectively reducing ja and jb . in addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces the ja . thermal performance for actual applications requires careful inspection of the conditions in an application. the use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in table 6. table 7. thermal resistance values pcb type airflow velocity (m/sec) ja jb jc_top jc_bot unit jedec 2s2p board 0.0 17.8 1, 2 6.3 1, 3 4.7 1, 5 1.2 1, 5 c/w 1.0 15.6 1, 2 5.9 1, 3 n/a 4 c/w 2.5 15.0 1, 2 5.7 1, 3 n/a 4 c/w 1 per jedec 51-7, plus jede c 51-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per jedec jesd51-8 (still air). 4 n/a = not applicable. 5 per mil-std 883, method 1012.1. esd caution
ad9234 data sheet pin configuration and function descriptions figure 5. pin configuration table 8 . pin function descriptions pin no. mnemonic type description power supplies 0 epad ground exposed pad. the exposed thermal pad on the bottom of the package provides the ground refe re nce for avdd x. this exposed pad must be connected to ground for proper operation. 1, 2, 47, 48, 49, 52, 55, 61, 64 avdd 1 supply analog power supply (1.2 5 v nominal). 3, 8, 9, 10, 11, 39, 40, 41, 46, 50, 51, 62, 63 avdd 2 supply analog power supply (2.5 v nominal). 4, 7, 42, 45 avdd3 supply analog power supply (3.3 v nominal) . 13, 38 spivdd supply digital power supply for spi (1.8 v to 3.3 v). 15, 34 d vdd supply digital power supply (1.2 5 v nominal). 16, 33 d gnd ground ground reference for dvdd. 18, 31 dr gn d ground ground reference for drvdd. 19, 30 d rvdd supply digital driver power supply (1.25 v nominal). 56, 60 agnd 1 ground ground reference for sysref . 57 avdd1_sr 1 supply analog power supply for sysref (1.25 v nominal). analog 5, 6 vin ? a, vin+a input adc a analog input complement /true. 12 v_1p0 input/dnc 1.0 v reference voltage input/do not connect. t his pin is configurable through the spi as a no connect or an input. d o not connect this pin if using the internal reference. this pin r equires a 1.0 v reference voltage input if using an external vo ltage reference source. 43, 4 4 vin+b , vin?b input adc b analog input true / complement . 53, 54 clk+, clk ? input clock input true/ complement . cmos output s 17, 32 fd_a, fd_b output fast detect outputs for channel a and channel b . ad9234 top view (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 fd_a drgnd drvdd syncinb? syncinb+ serdout0? serdout0+ serdout1? serdout1+ serdout2? serdout2+ serdout3? serdout3+ drvdd drgnd fd_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd1 avdd2 avdd2 avdd1 agnd sysref? sysref+ avdd1_sr agnd avdd1 clk? clk+ avdd1 avdd2 avdd2 avdd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd1 avdd1 avdd2 avdd3 vin?a vin+a avdd3 avdd2 avdd2 avdd2 avdd2 v_1p0 spivdd pdwn/stby dvdd dgnd avdd1 avdd1 avdd2 avdd3 vin?b vin+b avdd3 avdd2 avdd2 avdd2 spivdd csb sclk sdio dvdd dgnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 notes 1. the exposed thermal pad on the bottom of the package provides the ground refence for avddx. this exposed pad must be connected to ground for proper operation. 12244-005 rev. a | page 12 of 66
data sheet ad9234 pin no. mnemonic type description digital inputs 2 0, 2 1 syncinb ? , syncinb + input active low jesd204b lvds sync input complement/true . 58, 59 sysref+, sysref? input active high jesd204b lvds system reference input true/complement. data outputs 22, 23 serdout 0?, serdout0+ output lane 0 o utput data complement /true . 24, 25 serdout 1?, serdout1+ output lane 1 output data complement /true . 26, 27 serdout 2?, serdout2+ output lane 2 output data complement /true . 28, 29 serdout 3?, serdout3+ output lane 3 output data complement /true . d evice under test (d ut ) control s 14 pdwn /stby input power - down input (active high). the operation of this pin depends on the spi mode and can be configured as power - down or standby . 35 sdio input/o utput spi serial data i nput /o utput . 36 sclk input spi serial clock. 37 csb input spi chip select (active low). 1 to ensure proper a dc operation, connect avdd1_sr and agnd separate ly from the avdd1 and epad connection. for more information , refer to the applications information section . rev. a | page 13 of 66
ad9234 data sheet rev. a | page 14 of 66 typical performance characteristics ad9234-1000 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 1.34 v p-p full-scale differential input, a in = ?1.0 dbfs, default spi settings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. figure 6. single-tone fft with f in = 10.3 mhz figure 7. single-tone fft with f in = 170.3 mhz figure 8. single-tone fft with f in = 340.3 mhz figure 9. single-tone fft with f in = 450.3 mhz figure 10. single-tone fft with f in = 737.3 mhz figure 11. single-tone fft with f in = 985.3 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) 12244-100 a in = ?1dbfs snr = 64.2dbfs enob = 10.4bits sfdr = 88dbfs buffer current = 2.5 ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 63.9dbfs enob = 10.3 bits sfdr = 80dbfs buffer current = 2.5 12244-101 ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 63.4dbfs enob = 10.2 bits sfdr = 79dbfs buffer current = 3.0 12244-102 ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 63.1dbfs enob = 10.2 bits sfdr = 80dbfs buffer current = 4.5 12244-103 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 61.6dbfs enob = 9.9 bits sfdr = 81dbfs buffer current = 6.5 12244-300 ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 60.7dbfs enob = 9.8 bits sfdr = 79dbfs buffer current = 6.5 12244-301
data sheet ad9234 rev. a | page 15 of 66 figure 12. single-tone fft with f in = 1213.3 mhz figure 13. single-tone fft with f in = 1413.3 mhz figure 14. snr/sfdr vs. sample rate (f s ), f in = 170.3 mhz ; buffer current = 3.0 figure 15. snr/sfdr vs. input frequency (f in ); f in < 500 mhz ; buffer current = 3.5 (uses circuit shown in figure 63) figure 16. snr/sfdr vs. input frequency (f in ); 450 mhz < f in < 1500 mhz; buffer current = 7.5 (uses circuit shown in figure 64) figure 17. snr/sfdr vs. input frequency (f in ); 1500 mhz < f in < 2000 mhz; buffer current = 8.5 (uses circuit shown in figure 64) ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 59.7dbfs enob = 9.6 bits sfdr = 80dbfs buffer current = 7.0 12244-302 ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 58.8dbfs enob = 9.5 bits sfdr = 78dbfs buffer current = 7.5 12244-303 snr/sfdr (dbfs) sample rate (mhz) 60 70 80 90 700 750 800 850 900 950 1000 1050 1100 snr (dbfs) sfdr (dbfs) 12244-304 snr/sfdr (dbfs) input frequency (mhz) 60 70 80 90 snr (dbfs) sfdr (dbfs) 10.3 85.3 128.3 180.3 242.3 309.3 361.3 420.3 480.3 12244-306 snr/sfdr (dbfs) input frequency (mhz) 50 60 70 80 90 snr (dbfs) sfdr (dbfs) 453.3 629.3 737.3 837.3 937.3 1077.3 1177.3 1277.3 1377.3 1477.3 12244-307 snr/sfdr (dbfs) input frequency (mhz) 50 60 70 80 snr (dbfs) sfdr (dbfs) 1523.3 1587.3 1623.3 1687.3 1723.3 1787.3 1823.3 1887.3 1923.3 1987.3 12244-308
ad9234 data sheet rev. a | page 16 of 66 figure 18. two-tone fft; f in1 = 184 mhz, f in2 = 187 mhz figure 19. two-tone fft; f in1 = 338 mhz, f in2 = 341 mhz figure 20. two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz figure 21. two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 338 mhz and f in2 = 341 mhz figure 22. snr/sfdr vs. analog input level, f in = 10.3 mhz; buffer current = 2.0 figure 23. snr/sfdr vs. temperature, f in = 170.3 mhz amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0500 400 300 200 100 a in1 and a in2 = ?7dbfs sfdr = 81dbfs imd2 = 81dbfs imd3 = 83dbfs buffer current = 4.5 12244-205 amplitude (dbfs) frequency (mhz) ?150 ?135 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 0 0500 400 300 200 100 a in1 and a in2 = ?7dbfs sfdr = 78dbfs imd2 = 78dbfs imd3 = 85dbfs buffer current = 4.5 12244-206 ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 imd3 (dbfs) sfdr (dbfs) sfdr (dbc) imd3 (dbc) 12244-207 ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbc) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) 12244-208 snr/sfdr (dbc and dbfs) input amplitude (dbfs) ?40 ?20 0 120 100 80 60 40 20 ?97 ?84 ?74 ?64 ?54 ?44 ?34 ?24 ?14 ?4 sfdr (dbfs) snr (dbfs) snr (dbc) sfdr (dbc) 12244-209 snr/sfdr (dbfs) temperature (c) 90 80 70 60 sfdr snr ?45?35?25?15?5 5 1525354555657585 12244-400
data sheet ad9234 rev. a | page 17 of 66 figure 24. inl, f in = 10.3 mhz figure 25. dnl, f in = 10 mhz figure 26. input-referred noise histogram figure 27. power dissipation vs. temperature figure 28. power dissipati on vs. sample rate (f s ) inl (lsb) output code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 04000 3500 3000 2500 2000 1500 1000 500 12244-401 dnl (lsb) output code ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 04000 3500 3000 2500 2000 1500 1000 500 12244-402 number of hits output code n ? 3 n + 3 n + 2 n + 1 n n ? 1 n ? 2 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 1.02 lsb rms 12244-403 power dissipation (w) temperature (c) 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 ?45?35?25?15?5 5 1525354555657585 12244-404 power dissipation (w) sample rate (mhz) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 700 740 780 820 860 900 940 980 1020 1060 1110 12244-405
ad9234 data sheet rev. a | page 18 of 66 ad9234-500 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 1.63 v p-p full-scale differential input, a in = ?1.0 dbfs, default spi settings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. figure 29. single-tone fft with f in = 10.3 mhz figure 30. single-tone fft with f in = 170.3 mhz figure 31. single-tone fft with f in = 340.3 mhz figure 32. single-tone fft with f in = 450.3 mhz figure 33. single-tone fft with f in = 737.3 mhz figure 34. single-tone fft with f in = 985.3 mhz 12244-030 amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 frequency (mhz) a in = ?1dfbs snr = 65.9dbfs enob = 10.7bits sfdr = 85dbfs buffer current = 2.5 12244-506 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 a in = ?1dfbs snr = 65.9dbfs enob = 10.6bits sfdr = 85dbfs buffer current = 2.5 12244-507 amplitude (dbfs) a in = ?1dfbs snr = 65.5dbfs enob = 10.5bits sfdr = 86dbfs buffer current = 4.5 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250 12244-508 amplitude (dbfs) ain = ?1dfbs snr = 65.3dbfs enob = 10.5bits sfdr = 86dbfs buffer current = 4.5 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250 12244-509 amplitude (dbfs) ain = ?1dfbs snr = 64.2dbfs enob = 10.3bits sfdr = 75dbfs buffer current = 4.5x ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250 12244-510 amplitude (dbfs) ain = ?1dfbs snr = 63.6dbfs enob = 10.2bits sfdr = 75dbfs buffer current = 5.5 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250
data sheet ad9234 rev. a | page 19 of 66 figure 35. single-tone fft with f in = 1213.3 mhz figure 36. single-tone fft with f in = 1413.3 mhz figure 37. snr/sfdr vs. sample rate (f s ), f in = 170.3 mhz ; buffer current = 3.0 figure 38. snr/sfdr vs. input frequency (f in ); f in < 500 mhz; buffer current = 2.5 and 4.5 (uses circuit shown in figure 63) figure 39. snr/sfdr vs. input frequency (f in ); 450 mhz < f in < 1500 mhz; buffer current = 6.5 and 8.5 (uses circuit shown in figure 64) figure 40. snr/sfdr vs. input frequency (f in ); 1500 mhz < f in < 2000 mhz; buffer current = 8.5 (uses circuit shown in figure 64) 12244-511 amplitude (dbfs) ain = ?1dfbs snr = 62.9dbfs enob = 10.0bits sfdr = 72dbfs buffer current = 8.5 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250 12244-512 amplitude (dbfs) ain = ?1dfbs snr = 62.2dbfs enob = 9.9bits sfdr = 71dbfs buffer current = 8.5 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 0 50 100 150 200 250 12244-513 snrfs/sfdr (dbfs) frequency (mhz) 60 70 80 90 300 320 340 360 380 400 420 440 460 480 500 520 540 sfdr (dbfs) snrfs (dbfs) 12244-515 snr/sfdr (dbfs) frequency (mhz) 60 70 80 90 10.3 65.3 95.3 125.3 150.3 170.3 180.3 210.3 240.3 270.3 301.3 330.3 340.7 360.3 390.3 420.3 450.3 480.3 snr (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbfs) 450.3 480.3 510.3 515.3 610.3 765.3 810.3 985.3 1010.3 1110.3 1205.3 1310.3 1410.3 1510.3 12244-516 snf/sfdr (dbfs) frequency (mhz) 60 70 80 90 snr (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbfs) 12244-517 snr/sfdr (dbfs) frequency (mhz) 54 56 58 60 62 64 66 68 70 72 1510.3 1600.3 1710.3 1810.3 1910.3 1950.3 snr (dbfs) sfdr (dbfs)
ad9234 data sheet rev. a | page 20 of 66 figure 41. two-tone fft; f in1 = 184 mhz, f in2 = 187 mhz figure 42. two-tone fft; f in1 = 338 mhz, f in2 = 341 mhz figure 43. two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz figure 44. two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 338 mhz and f in2 = 341 mhz figure 45. snr/sfdr vs. analog input level, f in = 10.3 mhz; buffer current = 2.0 figure 46. snr/sfdr vs. temperature, f in = 170.3 mhz 12244-518 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 a in 1 and a in 2 = ?7dbfs sfdr = 90dbfs imd2 = 99dbfs imd3 = 90dbfs buffer current = 2.0 12244-519 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 a in 1 and a in 2 = ?7dbfs sfdr = 86dbfs imd2 = 86dbfs imd3 = 76dbfs buffer current = 4.5 12244-520 sfdr/imd3 (dbc and dbfs) amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr (dbc) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) 12244-521 sfdr/imd3 (dbc and dbfs) amplitude ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr (dbc) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) 12244-522 snr/sfdr (dbc and dbfs) amplitude (dbfs) ?40 ?20 0 20 40 60 80 100 120 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr (dbc) snr (dbfs) sfdr (dbc) sfdr (dbfs) 12244-523 snr/sfdr (dbfs) temperature (c) 60 70 80 90 100 ?45?25?15?51525456585 snrfs (dbfs) sfdr (dbfs)
data sheet ad9234 rev. a | page 21 of 66 figure 47. inl, f in = 10.3 mhz figure 48. dnl, f in = 10 mhz figure 49. input-referred noise histogram figure 50. power dissipation vs. temperature figure 51. power dissipati on vs. sample rate (f s ) 12244-524 inl (lsb) output code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 12244-525 dnl (lsb) output code ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 500 1000 1500 2000 2500 3000 3500 4000 12244-526 number of hits output code 0 200,000 400,000 600,000 800,000 1,000,000 1,200,000 1,400,000 1,600,000 1,800,000 2,000,000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 12244-527 dut powe r temperature (c) 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 2.12 2.13 2.14 ?45 ?25 ?15 ?5 15 25 45 65 85 12244-528 power dissipation (w) sample rate (mhz) 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 300 350 400 450 500 550 l.m.f = 4.2.1 l.m.f = 2.2.2
ad9234 data sheet equivalent circuits figure 52 . analog inputs figure 53 . clock inputs figure 54 . sysref inputs figure 55 . digital outputs figure 56 . syncinb inputs figure 57 . sclk input a in control (spi) 10pf vin+x vin?x avdd3 avdd3 avdd3 v cm buffer 400 200 200 67 28 200 200 67 28 avdd3 avdd3 3pf 3pf 12244-0 1 1 clk+ clk? avdd1 25? avdd1 25? 20k? 20k? v cm = 0.85v 12244-012 sysref+ avdd1_sr 1k? sysref? avdd1_sr 1k? 20k? 20k? level translator v cm = 0.85v 12244-013 drvdd drgnd drvdd drgnd output driver emphasis/swing control (spi) data+ data? serdoutx+ x = 0, 1, 2, 3 serdoutx? x = 0, 1, 2, 3 12244-014 20k? 20k? level translator v cm = 0.85v syncinb pin control (spi) syncinb+ dvdd 1k? dgnd syncinb? dvdd 1k? dgnd v cm 12244-015 30k spivdd esd protected esd protected 1k? spivdd sclk 12244-016 rev. a | page 22 of 66
data sheet ad9234 figure 58 . csb input figure 59 . sdio input figure 60 . fd_a/fd_b outputs figure 61 . pdwn/stby input figure 62 . v_1p0 input 30k esd protected esd protected 1k? spivdd csb 12244-017 30k esd protected esd protected 1k? spivdd spivdd sdi sdio sdo 12244-018 esd protected esd protected spivdd fd_a/fd_b fd jesd lmfc fd_x pin control (spi) jesd sync~ temperature diode (fd_a only) 12244-019 30k esd protected esd protected 1k? spivdd pdwn/ stby pdwn control (spi) 12244-020 esd protected esd protected v_1p0 v_1p0 pin control (spi) avdd2 12244-021 rev. a | page 23 of 66
ad9234 data sheet theory of operation the ad9234 has two analog input channels and four jesd204b output lane pairs. the adc is designed to sample wide band - width analog signals of up to 2 ghz. the ad9234 is optimized for wide input bandw idth, high sampling rate, excellent linearity , and low power in a small package. the dual adc cores feature a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. the ad9234 has several functions that simplify the agc function in a com munications receiver . the programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the adc. if the input signal level exceeds the programmable threshold, the fast detect indicator goes high. because this threshold ind icator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the adc input. the subclass 1 jesd204b - based high speed serialized output data rate can be configured in one - lane (l = 1 ), two - lane (l = 2) , and four - lane (l = 4) configurations , depending on the sample rate and the decimation ratio. multi ple device synchronization is supported through the sysref and syncinb input pins. adc architecture the architecture of the ad9234 consists of an input buffered pipelined adc. the input buffer is designed to provide a termination impedance to the analog input signal. this ter - mination impedance can be changed using the s pi to meet the termination needs of the driver/amplifier . the default termination value is set to 400 . the equivalent circuit diagram of the analog input termination is shown in figure 52. the input buffer is optimized for high linearity, low noise , and low power. the input buffer provides a linear high input impedance (for ease of drive) and reduces kick back from the adc. the buffer is optimized fo r high linearity, low noise, and low power. the quantized outputs from each stage are combined into a final 12- bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample ; at the same ti me, the remaining stages operate with the preceding samples. sampling occurs on the rising edge of the clock. analog input conside rations the analog input to the ad9234 is a different ial buffer. the internal common - mode voltage of the buffer is 2.05 v . the clock signal alternately switches the input circuit between sample mode and hold mode. when the input circuit is switched into sample mode, the signal source must be capable of charging the samp le capacitors and settling within one - half of a clock cycle. a small resistor, in series with each input, help s reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be pla ced on each leg of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequenc ies. either a differential capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the input, which limits unwanted broadband noise. for more information, refe r to the an - 742 application note , the an - 827 application note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) . in general, the precise values depend on the application. for best dynamic performance, the source impedances driving vin+ x and vin? x must be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. an internal reference buffer creates a differential reference that defines the span of the adc core. maximum snr perfo rmance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9234 , the available span is 1.34 v p - p differential for ad9234 - 1000 and 1.63 v p - p differential for ad9234 - 500. differential input configurations there are several ways to drive the ad9234 , either actively or passively. however, optimum performance is achieved by driving the analog i nput differentially. for applications where snr and sfdr are key parameters, differential transformer coupling is the recommended i nput configuration (see figure 63 and figure 64 ) because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9234 . for low to mid range frequencies, a double balun or do uble transformer network (see figure 63) is recommended for optimum performance of the ad9234 . f or hig her frequencies in the second and third nyquist zone s , it is better to remove some of the front - end passive com ponents to ensure wide band operation (see figure 64) . rev. a | page 24 of 66
data sheet ad9234 figure 63 . differential transformer - coupled configuration for frequencies up to 500 mhz figure 64 . differential transformer - coupled configuration for frequencies > 500 mhz input common mode the analog inputs of the ad9234 are internally biased to the common mode as shown in figur e 65 . the common - mode buffer has a limited range in that the performance suffers greatly if the common - mode voltage drops by more than 100 m v. therefore, in dc - coupled applications, set the common - mode voltage to 2.05 v, 100 mv to ensure proper adc operation. analog input controls and sfdr optimization the ad9234 offers flexible controls for the analog inputs , such as input term ination and buffer current. all of the available controls are show n in figure 65 . figure 65 . analog input controls using register 0x 0 18, the buffer currents on each channel can be scaled to optimize the sfdr over various input frequencies and bandwidths of interest. as the input buffer currents are set, the amount of current required by the avdd3 supply changes . this relatio nship is shown in figure 66 . for a complete list of buffer current settings, see table 22. figure 66 . avdd3 power (i avdd3 ) vs. buffer current setting adc 2pf 10? 10? 4pf 0.1f 0.1f 10? 10? 4pf 0.1f 25? 25? etc1-11-13/ maba007159 1:1z 12244-022 adc 25? 0.1f 0.1f 25? 0.1f 25? 25? marki bal-0006 or bal-0006smg 12244-023 a in control (spi) registers (0x008, 0x015, 0x016, 0x018) 10pf vin+x vin?x avdd3 avdd3 avdd3 v cm buffer 400 200 200 67 28 200 200 67 28 3pf 3pf avdd3 avdd3 12244-027 i avdd3 (ma) buffer control 1 setting 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 12244-341 50 100 150 200 250 300 ad9234-1000 ad9234-500 rev. a | page 25 of 66
ad9234 data sheet figure 67, figure 68 , and figure 69 show how the sfdr for ad9234 - 1000 can be optimized using the buffer current setting in regis ter 0x018 for different nyquist zones. figure 70 , figure 71, and figure 72 show how the sfdr for ad9234 - 500 can be optimized using the buffer current setting in register 0x018 for different nyquist zones. at frequencies greater than 1 ghz, it is better to run the adc at input amplitudes less than ?1 dbfs (?3 dbfs, for example). this greatly improves the linearity of the converted signal without sacrificing snr performance. fi gure 67 . buffer current sweeps, ad9234 - 1000 ; sfdr vs. input frequency ( i buff ); f in < 500 mhz figure 68 . buffer current sweeps, ad9234 - 1000 ; sfdr vs. input frequency ( i buff ) ; 500 mhz < f in < 1500 mhz figure 69 . buffer current sweeps, ad9234 - 1000 ; sfdr vs. input frequency ( i buff ); 1500 mhz < f in < 2000 mhz figure 70 . buffer current sweeps, ad9234 - 500 ; sfdr vs. input frequency (i buff ); f in < 500 mhz figure 71 . buffer current sweeps, ad9234 - 500 ; sfdr vs. input frequency (i buff ); 500 mhz < f in < 1500 mhz 90 50 55 60 65 70 75 80 85 sfdr (dbfs) input frequency (mhz) 10.3 85.3 128.3 180.3 242.3 309.3 361.3 420.3 480.3 1.5 2.5 3.5 4.5 12244-342 90 50 55 60 65 70 75 80 85 sfdr (dbfs) input frequency (mhz) 453.3 629.3 737.3 837.3 937.3 1077.3 1177.3 1277.3 1377.3 1477.3 4.5 5.5 6.5 7.5 8.5 12244-343 80 75 70 30 35 40 45 50 55 60 65 sfdr (dbfs) input frequency (mhz) 1523.3 1587.3 1623.3 1687.3 1723.3 1787.3 1823.3 1887.3 1923.3 1987.3 5.5 6.5 7.5 8.5 12244-344 12244-529 sfdr (dbfs) frequency (mhz) 50 55 60 65 70 75 80 85 90 95 10.3 65.3 95.3 125.3 150.3 170.3 180.3 210.3 240.3 270.3 301.3 330.3 340.7 360.3 390.3 420.3 450.3 480.3 3.5 1.5 2.5 4.5 2.0 12244-530 sfdr (dbfs) frequency (mhz) 50 55 60 65 70 75 80 85 90 450.3 480.3 510.3 515.3 610.3 765.3 810.3 985.3 1010.3 1110.3 1205.3 1310.3 1410.3 1510.3 7.5 6.5 5.5 4.5 8.5 rev. a | page 26 of 66
data sheet ad9234 figure 72 . buffer current sweeps, ad9234 - 500 ; sfdr vs. input frequency (i buff );1500 mhz < f in < 2000 mhz table 9 shows the recommended buffer current and full - scale voltage settings for the different analog input frequency ranges. table 9 . sfdr optimization for input frequencies input frequency input buffer current control setting, register 0x018 <400 mhz 2.5 or 3.0 400 mhz to 1 ghz 4.5 or 6.5 >1 ghz 6.5 or higher absolute maximum input swing the absolute maximum input swing allowed at the inputs of the ad9234 is 4.3 v p - p differential. signals operating near or at this level can cause permanent damage to the adc. voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9234 . this internal 1.0 v reference is used to set the full - scale input range of the adc. for more information on adjusting the input swing, see table 22 . figure 73 shows the block diagram of the internal 1.0 v reference controls. figure 73 . internal reference configuration and controls the spi r egister 0x 024 enables the user to either use this internal 1.0 v reference , or to provide an external 1.0 v reference. when using an external voltage reference, provide a 1.0 v reference. the use of an external reference may be necessary , in some applications, to enhance the gain accuracy of the adc or improve thermal drift charac teristics. figure 74 shows the typical drift characteristics of the internal 1.0 v reference . figure 74 . typical v_1p0 drift the external reference must be a stable 1.0 v reference. the adr130 i s a good option for providing the 1.0 v reference. figure 75 shows how the adr130 can be used to provide the external 1.0 v reference to the ad9234 . the grayed out are as show unused blocks within the ad9234 while using the adr130 to provide the external reference. figure 75 . external reference using adr130 12244-531 sfdr (dbfs) frequency (mhz) 52 54 56 58 60 62 64 66 68 70 72 1510.3 1600.3 1710.3 1810.3 1910.3 1950.3 6.5 7.5 8.5 adc core full-scale voltage adjust v_1p0 pin control spi register (0x024) v_1p0 vin?a/ vin?b vin+a/ vin+b internal v_1p0 generator v_1p0 adjust spi register (0x024) 12244-031 ?50 0 25 90 v_1p0 voltage (v) temperature (c) 0.9998 0.9999 1.0000 1.0001 1.0002 1.0003 1.0004 1.0005 1.0006 1.0007 1.0008 1.0009 1.0010 12244-106 v_1p0 adjust v_1p0 0.1f v out 4 set 5 nc 6 v in 3 gnd 2 nc 1 adr130 0.1f input v_1p0 adjust internal v_1p0 generator 12244-032 rev. a | page 27 of 66
ad9234 data sheet clock input consider ations for optimum performance, drive the ad9234 sample clock inputs (clk+ and clk? ) with a differential signal. this s ignal is typically ac - coupled to the clk+ and clk? pins via a transformer or clock driver s. these pins are biased internally and require no additi onal bias ing . figure 76 shows a preferred method for clocking the ad9234 . the low jitter clock source is converted from a single - ended signal to a differential signal using an rf transformer. figure 76 . transformer - coupled differential clock a nother option is to ac couple a differential cml or lvds signal to the sample clock input pins , as shown in figure 77 and figure 78. figure 77 . differential cml sample clock figure 78 . differential lvds sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance charac teristics. in applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. the ad9234 can be clocked at 2 ghz with the internal clock divider set to 2. the output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal adc . see the memory map section for more details on using this feature. input clock divider the ad9234 contains an input clock divid er with the ability to divide the nyquist input clock by 1, 2, 4 , and 8 . the divider ratios ca n be selected using register 0x 10b . this is shown in figure 79. the maximum frequency at the clk inputs is 4 ghz. this is the limit of the divider. in applications where the clock input is a multiple of the sample clock, care must be taken to program the appropriate divider ratio into the clock divider before applying the clock signal. this ensures that the current transients during device st artup are controlled. figure 79 . clock divider circuit the ad9234 clock divider can be synchronized using the external sysref input. a valid sysref causes the clock di vider to reset to a programmable state. this feature is enabled by setting bit 7 of register 0x10d. this synchro nization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. see the multic hip synchronization section for more information input clock divider ? period delay adjust the input clock divider inside the ad9234 provides phase delay in increments of ? the input clock cycle. register 0x10c can be programmed to enable this delay independently for each channel. changing this register does not affect the stability of the jesd204b link. clock fine delay adjust the ad9234 sampling edge instant can be adjusted by writing to register 0x117 and register 0x118. setting bit 0 of register 0x117 enables the feature , and register 0x118 , bits[7:0] set the value of the delay. this value can be programmed indi - vidually for each channel . the clock delay can be adjusted from ? 151.7 ps to +150 ps in ~1.7 ps increments. the clock delay adjust take s effect immediately when it is enabled via spi writes. enabling the clock fine delay adjust in register 0x117 cause s a data path reset. however, the contents of register 0x118 can be changed without affecting the stability of the jesd204b link. adc clk+ clk? 0.1f 0.1f 100? 50? clock input 1:1z 12244-035 adc clk+ clk? 0.1f 0.1f z0 = 50 z0 = 50 33? 33? 71? 10pf 3.3v 12244-036 adc clk+ clk? 0.1f 0.1f 0.1f 0.1f 50? 1 50? 1 100? clock input lvds driver clk+ clk? 1 50 resistors are optional. clock input 12244-037 clk+ clk? 2 4 reg 0x10b 8 12244-038 rev. a | page 28 of 66
data sheet ad9234 clock jitter considerations high spee d, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr = 20 log 10 (2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc ape rture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 80). figure 80 . ideal snr vs. analog input frequency and jitter t reat t he clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9234 . separate p ower supplies for clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. if the clock is g enerated from another type of so urce (by gating, dividing, or other methods ), retime the clock by the original clock at the last step. refer to the an - 501 application note and the an - 756 application note for more in - depth information about jitter performance as it relates to adcs. power - down/ standby mode the ad9234 has a pdwn/stby pin that can be used to configure the device in power - down or standby mode. the default operation is the pdwn function . the pdwn/stby pin is a logic high pin. when in power - down mode, the jesd204b link is disrupted. the power - down option can also be set via register 0x03f and register 0x040. in standby mode, the jesd204b link is not disrupted and transmits zeroes for all converter samples. this can be changed using register 0x571, bit 7 to select /k/ characters. temp erature diode the ad9234 contains a diode - based temperature sensor for measuring the temperature of the die. th is diode can output a voltage and serve a s a coarse temperature sensor to monitor the internal die temperature. the temperature diode voltage can be output to the fd_a pin using the spi. use r egister 0x028 , bit 0 to enable or disable the diode. register 0x028 is a local register. channel a must be selected in the device index register ( register 0x008) to en able the temperature diode read out. c onfigure the fd_a pin to output the diode voltage by programming r egister 0x040 [2:0] . s ee table 22 f or more information. the voltage response of th e temperature diode (spivdd = 1.8 v) is shown in figure 81. figure 81 . diode voltage vs. temperature 130 120 110 100 90 80 70 60 50 40 30 10 100 1000 10000 snr (db) analog input frequency (mhz) 12.5 f s 25 f s 50 f s 100 f s 200 f s 400 f s 800 f s 12244-039 diode voltage (v) temperature (c) 0.60 0.65 0.70 0.75 0.80 0.85 0.90 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 115 125 12244-353 rev. a | page 29 of 66
ad9234 data sheet rev. a | page 30 of 66 adc overrange and fast detect in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overrange bit in the jesd204b outputs provides information on the state of the analog input that is of limited usefulness. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. in addition, because input signals can have significant slew rates, the latency of this function is of major concern. highly pipelined converters can have significant latency. the ad9234 contains fast detect circuitry for individual channels to monitor the threshold and assert the fd_a and fd_b pins. adc overrange the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange indicator can be embedded within the jesd204b link as a control bit (when csb > 0). the latency of this overrange indicator matches the sample latency. the ad9234 also records any overrange condition in any of the four virtual converters. for more information on the virtual converters, refer to figure 87. the overrange status of each virtual converter is registered as a sticky bit in register 0x563. the contents of register 0x563 can be cleared using register 0x562, by toggling the bits corresponding to the virtual converter to set and reset position. fast threshold detection (fd_a and fd_b) the fd bit (enabled via the control bits in register 0x559 and register 0x55a) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. the fd bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. this feature provides hysteresis and prevents the fd bit from excessively toggling. the operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in figure 82. the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at register 0x247 and register 0x248. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshold detection has a latency of 28 clock cycles (maximum). the approximate upper threshold magnitude is defined by upper threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 13 ) the fd indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. the lower threshold is programmed in the fast detect lower threshold registers, located at register 0x249 and register 0x24a. the fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the adc. this comparison is subject to the adc pipeline latency, but is accurate in terms of converter resolution. the lower threshold magnitude is defined by lower threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 13 ) for example, to set an upper threshold of ?6 dbfs, write 0xfff to register 0x247 and register 0x248. to set a lower threshold of ?10 dbfs, write 0xa1d to register 0x249 and register 0x24a. the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at register 0x24b and register 0x24c. see the memory map section (register 0x040, and register 0x245 to register 0x24c in table 22) for more details. figure 82. threshold settings for fd_a and fd_b signals upper threshold lower threshold fd_a or fd_b midscale dwell time timer reset by rise above lower threshold timer completes before signal rises above lower threshold dwell time 12244-040
data sheet ad9234 signal monitor the signal monitor block provides additional information about the signal being digitized by the adc. the signal monitor computes the peak magnitude of the digitized signal . this information can be used to drive an agc loop to optimize the range of the adc in the presence of real - world signals. the results of the signal monitor block can be obtained eithe r by reading back the internal values from the spi port or by embedding the signal monitoring information into the jesd204b inte rface as special control bits. a global, 24 - bit programmable period controls the duration of the measure - ment. figure 83 shows the simplified block diagram of the signal monitor block. figure 83 . signal monitor block the peak detector captures the lar gest signal within the observation period. the detector only observe s the magnitude of the signal. the resolution of the peak detector is a 13 - bit value and the observation period is 24 bits and represents converter output samples . the peak magnitude can b e derived by using the following equation: peak magnitude (dbfs) = 20 log ( peak detector value /2 13 ) the magnitude of the input port signal is monitored o ver a programmable time period, which is determined by the signal monitor p eriod r egister (smpr). the peak detector function is enabled by setting b it 1 of register 0x270 in the si gnal monitor control register. the 24 - bit smpr must be programmed before activating this mode. after enabling this mode, the value in the smpr is loaded into a moni tor period timer , which decrements at the decimated clock rate. the magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. the initial value of the magnitude storage register is set to the current adc input signal magnitude. this com - parison continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the 13 - bit pea k level value is transferred to the s ignal monitor holding register, which can be read through the memory map or output through the sport over the jesd204b interface. the monitor period timer is reloaded with the value in the smpr, and the countdown is res tarted. in addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. sport o ver jesd204b the signal monitor data can also be serialized and s ent over the jesd2 04b interface as control bits. these control bits must be de serialized from the samples to reconstruct the statistical data. this fun ction is enabled by setting bit 1 and bit 0 of register 0x279 and b it 1 of register 0x27a. figure 84 shows two differ - ent example configurations for the signal monitor control bit locations inside the jesd204b s amples. there are a maximum of three control bits that can be inserted into the jesd 204b samples; however , only one control bit is required for the signal monitor. control bits are inserted from msb to lsb. if only one control bit is to be inserted (cs = 1), then only the most signif ic ant control bit is used (see example c onfiguration 1 and example c onfiguration 2 in figure 84 ). to select the sport over jesd 204b option, program register 0x559, register 0x 55a , and register 0x58f. see table 22 for more inf ormation on setting these bits. figure 85 shows the 25 - bit f rame data that encaps ulates the peak detector v alue. the frame data is transmitted msb first with five 5 - bit subframes . ea ch sub frame contains a start bit that can be used b y a receiver to validate the de serialized data. figure 86 shows the sport over jesd204b signal m onitor data with a monitor period timer set to 80 samples. from memory map down counter is count = 1? magnitude storage register from input signal monitor holding register load clear compare a > b load load to sport over jesd204b and memory map signal monitor period register (smpr) 0x271, 0x272, 0x273 12244-406 rev. a | page 31 of 66
ad9234 data sheet figure 84 . signal monitor control bit locations figure 85 . sport over jesd204b signal monitor frame data 15 14-bit converter resolution (n = 14) tail x 1 control bit (cs = 1) 1-bit control bit (cs = 1) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 tail bit serialized signal monitor frame data example configuration 1 (n' = 16, n = 15, cs = 1) example configuration 2 (n' = 16, n = 14, cs = 1) serialized signal monitor frame data 16-bit jesd204b sample size (n' = 16) s[13] x s[12] x s[11] x s[10] x s[9] x s[8] x s[7] x s[6] x s[5] x s[4] x s[3] x s[2] x s[1] x s[0] x ctrl [bit 2] x ctrl [bit 2] x s[14] x s[13] x s[12] x s[11] x s[10] x s[9] x s[8] x s[7] x s[6] x s[5] x s[4] x s[3] x s[2] x s[1] x s[0] x 15-bit converter resolution (n = 15) 16-bit jesd204b sample size (n' = 16) 12244-407 25-bit frame 5-bit idle sub-frame (optional) 5-bit identifier sub-frame 5-bit data msb sub-frame 5-bit data sub-frame 5-bit data sub-frame 5-bit data lsb sub-frame 5-bit sub-frames p[] = peak magnitude value idle 1 idle 1 idle 1 idle 1 idle 1 start 0 p[0] 0 0 0 start 0 p[4] p[3] p[2] p1] start 0 p[8] p[7] p[6] p5] start 0 p[12] p[11] p[10] p[9] start 0 id[3] 0 id[2] 0 id[1] 0 id[0] 1 12244-408 rev. a | page 32 of 66
data sheet ad9234 figure 86 . sport over jesd204b signal monitor example with period = 80 samples payload #3 25-bit frame (n) payload #3 25-bit frame (n + 1) payload #3 25-bit frame (n + 2) idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb smpr = 80 samples (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00) 80 sample period 80 sample period 80 sample period 12244-409 rev. a | page 33 of 66
ad9234 data sheet digital downconverte r (ddc) the ad9234 inclu des two digital do wnconverters (ddc 0 and ddc 1 ) that provide filtering and reduce the output data rate. this digital processing section includes a half - band decimating filter, a gain stage , and a complex to real conversion stage. each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired p rocessing function. the digital downconverter can be configured to output either real data or complex output data . ddc general descript ion the two ddc blocks are used to extract a portion of the full digital spectrum captured by the adc(s). they are intended for if sampling or oversampled baseband radios requiring wide bandwidth input signals. each ddc block contains a decimate - by - 2 digital processing block , as shown in figure 87. when ddcs have different d ecimation ratios, the chip decima - tion ratio (r egister 0x 201) must be set to the lowest decimation r atio of all the ddc blocks. in this scenario, samples of higher decimation ratio ddcs are repeated to match the chip decima - tion ratio sample rate. whenever the nco frequency is set or changed, the ddc soft reset must be issued. if the ddc soft reset is no t issued, the output may potentially show amplitude variations. th e ddcs output a 16 - bit stream. t o enable this operation , the converter number of bits n is set to a default value of 16, even though the analog core only outputs 12 bits . figure 87 . ddc detailed block diagram ddc 0 real/i converter 0 q converter 1 real/i hb1 fir dcm = 2 real/i converter 2 q converter 3 real/q ddc 1 real/i hb1 fir dcm = 2 real/q i q i q i/q crossbar mux adc a sampling at f s real/i adc b sampling at f s real/q output interface 12244-161 rev. a | page 34 of 66
data sheet ad9234 half - band filter the ad9234 offers one half - band filter per ddc to enable digital signal processing of the adc converted data. the decimate - by - 2, half - band (hb), low - pass fir filter uses a 55- tap, symmetrical, fixed coefficient filter implementation, optimized for low power consump tion. the hb filter is enabled when the ddc is selected. table 10 and figure 88 show the coefficients and response of the hb1 filter. figure 88 . hb1 filter response table 10 . half - band filter coefficients hb1 coefficient number normalized coefficient decimal coefficient (21 - bit) c1, c55 ?0.000023 ?24 c2, c54 0 0 c3, c53 0.000097 102 c4, c52 0 0 c5, c51 ?0.000288 ?302 c6, c50 0 0 c7, c49 0.000696 730 c8, c48 0 0 c9, c47 ?0.0014725 ?1544 c10, c46 0 0 c11, c45 0.002827 2964 c12, c44 0 0 c13, c43 ?0.005039 ?5284 c14, c42 0 0 c15, c41 0.008491 8903 c16, c40 0 0 c17, c39 ?0.013717 ?14,383 c18, c38 0 0 c19, c37 0.021591 22640 c20, c36 0 0 c21, c35 ?0.033833 ?35476 c22, c34 0 0 c23, c33 0.054806 57468 c24, c32 0 0 c25, c31 ?0. 100557 ?105442 c26, c30 0 0 c27, c29 0.316421 331,792 c28 0.500000 524,288 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 magnitude (db) normalized frequency ( rad/sample) 12244-048 rev. a | page 35 of 66
ad9234 data sheet ddc gain stage each ddc contains an independently controlled gain stage. the gain is selectable as either 0 db or 6 db. when mixing a real input signal down to baseband, it is recommended that the user enable the 6 db of gain to recenter the dynamic range of the signal within the full scale of the output bits. when mixing a complex input signal down to baseband, the mixer has already recenter ed the dynamic range of the signal within the full scale of the output bits and no additional gain is necessary. however, the optional 6 db gain can be used to compensate for low signal strengths. the downsample by 2 portion of the hb1 fir filter is bypas sed when using the complex to real conversion stage (see figure 89). ddc complex to real conversion each ddc contains an independently controlled comp lex to real conversion block. the complex to real conversion block reuses the last filter (hb1 fir) in the filtering stage, along with an f s /4 complex mixer , to upconvert the signal. after up converting the signal, the q portion of the complex mixer is no l onger needed and is dropped. figure 89 shows a simplified block diagram of the complex to real conversion. figure 89 . complex to real conversion block low-pass filter 2 i q real hb1 fir low-pass filter 2 hb1 fir 0 1 complex to real enable q 90 0 + ? complex to real conversion i q i q gain stage cos(wt) sin(wt) f s /4 i/real 0db or 6db 0db or 6db 0db or 6db 0db or 6db 12244-049 rev. a | page 36 of 66
data sheet ad9234 digital outputs introduction to the jesd204b interface the ad9234 digital outputs are designed to the jede c s tandar d jesd204b, serial interface for data converters . jesd204b is a protocol to link the ad9234 to a digital processing device over a serial interface with lane rates of up to 10 gbps. the ben efits of the jesd204b interface over lvds include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. jesd204b overview the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 b /10 b encoding as well as optional scrambling t o form serial output data. lane synchron - ization is supported through the us e of special control characters during the initial establishment of the link. additional control characters are embedded in the data stream to maintain synchro - n ization thereafter. a jesd204b receiver is required to complete th e serial link. for additional details on the jesd204b interface , users are encouraged to refer to the jesd204b standard. the ad9234 je sd204b data transmit block maps up to two physical a dcs or up to eight virtual converters (when ddcs are enabled) over a link. a link can be configured to use one, two , or four jesd204b lanes. the jesd204b specification refers to a number of parameters to define the link , and these parameters must match between the jesd204b transmitter ( the ad9234 output) and the jesd204b receiver ( the logic device input). the jesd204b link is described according to the following parameters: ? l = number of lanes/ converter device (l anes/ link) ( ad9234 value = 1, 2 , or 4) ? m = number of converters/converter device (virtual c onverters / link ) ( ad9234 value = 1, 2, 4 , or 8) ? f = octets/frame ( ad9234 value = 1, 2, 4, 8 , or 16) ? n ? = number of bits per sample (jesd 204b word size) ( ad9234 value = 8 or 16) ? n = converter resolution ( ad9234 value = 7 to 16) ? cs = number of control bits/sample ( ad9234 value = 0, 1, 2 , or 3 ) ? k = number of frames per multiframe ( ad9234 value = 4, 8, 12, 16, 20, 24, 28 , or 32 ) ? s = samples transmitted/single converter/frame cycle ( ad9234 value = s et automatically based on l, m, f , and n ?) ? hd = high densit y mode ( ad9234 = s et automatically based on l, m, f , and n ? ) ? cf = number of control words/frame clock cycle/converter device ( ad9234 value = 0) figure 90 sho ws a simplified block diagram of the ad9234 jesd204b link. by default, the ad9234 is configured to use two converters and four lanes. c onverter a data is output to serdout0 and / or serdout1 , and converter b is output to serdout2 and/or serdout3 . the ad9234 allows other co nfigurations such as combining t he outputs of both converters onto a single lane , or changing the mapping of the a and b digital output paths. these modes are set up via a quick configuration register in the spi register map, along with additional customizable options. by default in the ad9234 , the 12 - bit converter word from each converter is broken in to two octets (eight bits of data). bit 13 (msb) through bit 6 are in the first octet. the second octet contains bit 5 through bit 0 (lsb) and two t ail bits. the tail bits can be configured as zeros or a pseudo random number sequence. the tail bits can also be replaced with control bit s indicating overrange, sysref , signal monitor, or fast detect output . the two resulting octets can be scrambled. scr ambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. the scrambler uses a self - synchronizing , polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the recei ver is a self - synchronizing version of the scrambler polynomial. the two octets are then encoded with an 8 b /10 b encoder. the 8 b /10 b encoder works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 91 shows how the 12- bit data is taken from the adc, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10 - bit symbols. fig ure 91 illustrates the default data format. rev. a | page 37 of 66
ad9234 data sheet rev. a | page 38 of 66 figure 90. transmit link simplified block diagram showing full bandwidth mode (register 0x200 = 0x00) figure 91. adc output datapath showing data framing figure 92. data flow functional overview the block diagram in figure 92 shows the flow of data through the jesd204b hardware from the sample input to the physical output. the processing can be divided into layers that are derived from the open-source initiative (osi) model widely used to describe the abstraction layers of communications systems. these layers are the transport layer, data link layer, and physical layer (serializer and output driver). transport layer the transport layer handles packing the data (consisting of samples and optional control bits) into jesd204b frames that are mapped to 8-bit octets. these octets are sent to the data link layer. the transport layer mapping is controlled by rules derived from the link parameters. tail bits are added to fill gaps where required. the following equation can be used to determine the number of tail bits within a sample (jesd204b word): t = n? C n C cs data link layer the data link layer is responsible for the low level functions of passing data across the link. these include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, and encoding 8-bit octets into 10-bit symbols. the data link layer is also responsible for sending the initial lane alignment sequence (ilas), which contains the link configuration data used by the receiver to verify the settings in the transport layer. physical layer the physical layer consists of the high speed circuitry clocked at the serial clock rate. in this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. adc a adc b sysref syncinb converter a input converter b input converter 0 converter 1 serdout0?, serdout0+ serdout1?, serdout1+ serdout2?, serdout2+ serdout3?, serdout3+ lane mux and mapping (spi reg 0x5b0, reg 0x5b2, reg 0x5b3, reg 0x5b5, reg 0x5b6) jesd204b link control (l.m.f) (spi reg 0x570) mux/ format (spi reg 0x561, reg 0x564) 12244-050 8-bit/10-bit encoder serdout0 serdout1 tail bits 0x571[6] serializer adc symbol0 symbol1 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 c2 c1 c0 msb lsb control bits adc test patterns (re0x550, reg 0x551 to reg 0x558) jesd204b sample construction jesd204b interface test pattern (reg 0x573, reg 0x551 to reg 0x558) frame construction jesd204b data link layer test patterns reg 0x574[2:0] scrambler 1+x 14 +x 15 (optional) a13 a12 a11 a10 a9 a8 a6 a7 a5 a4 a3 a2 a1 a0 c2 t msb lsb octet 0 octet 1 s7 s6 s5 s4 s3 s2 s1 s0 s7 s6 s5 s4 s3 s2 s1 s0 msb lsb octet 0 octet 1 a b c d e f g h i j a b c d e f g h i j a b i j a b i j 12244-151 jesd204b long transport test pattern reg 0x571[5] transport layer physical layer data link layer tx output sample construction frame construction scrambler alignment character generation 8-bit/10-bit encoder crossbar mux serializer processed samples from adc sysref syncinb 12244-052
data sheet ad9234 jesd204b link establ ishment the ad9234 jesd204b transmitter ( tx ) interface operates in subclass 1 as defined in the jedec standard jesd 204b ( july 2011 specification ) . the link establishment process i s divided into the following steps: code group synchronization and syncinb , initial lane alignment sequence, and user dat a and error correction . code group synchronization (cgs) an d syncinb the cgs is the process by which the jesd204b receiver finds the boundaries between the 10 - bit symbols in the stream of data. during the cgs phase, the jesd204b transmit block transmits /k28.5/ characters . the receiver must locate / k28.5 / characters in its input data stream using clock and data recovery (cdr) techniques. the receiver issues a synchronization request by asserting the syncinb pin of the ad9234 low . the jesd 204b tx the n begin s sending /k/ characters. after the receiver has synchronized, it waits for the correct reception of at least four consecutive /k/ symbols. it then deasserts syncinb . the ad9234 then transmit s an ilas on the following local multiframe clock ( lmfc ) boundary . for more information on the code group synchronization phase, refer to the jedec standard jesd 204b, july 2011, section 5.3.3.1. the syncinb pin operation can also be cont rolled by the spi. the syncinb signal is a differential dc - c oupled lvds mode signal by default, but it can also be driven sin gle - ended. for more information on configuring the syncinb pin oper ation, refer to r egister 0x 572 . initial lane alignment sequence (ilas) the ilas phase follows the cgs phase and begin s on the next lmfc boundary. the ilas consists of four multi frames , with a n /r/ character marking the beginning and an /a / character marking the end. the ilas begins by sending an /r/ character followed by 0 to 255 ramp data for one multiframe. on the second multiframe , the link configuration data is sent , starting with the third character. the second character is a /q/ char acter to confirm that the link configuration data follow s . all undefined data slots are filled with ramp data. the ilas sequence is never scrambled. the ilas sequence construction is shown in figure 93 . the four multiframes include the following: ? multiframe 1. b egins with an /r/ character ( / k28.0 / ) and ends with an /a/ chara cter ( / k28.3 / ) . ? multif rame 2. b egins with an / r/ character followed by a /q/ ( / k28.4 / ) character, followed by link configuration parameters over 14 configuration octets (see table 11) and ends with an /a/ character. ma ny of the parameter values are of the value C 1 notation. ? multiframe 3. b egins with an /r/ character ( / k28.0 / ) and ends with an /a/ character ( / k28.3 / ) . ? multiframe 4. begins with an /r/ character ( / k28.0 / ) and ends with an /a/ character ( / k28.3 / ) . figure 93 . initial lane alignment sequence k k r d d a r q c c d d a r d d a r d d a d start of ilas start of link configuration data end of multiframe start of user data 12244-053 rev. a | page 39 of 66
ad9234 data sheet user data and error detection after the initial lane alignment sequence is complete, the user data is sent. normally, with i n a frame , all characters are considered user data . h owever , to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /f/ or /a/ alignment characters when the data meets certain conditions. these c onditions are different for unscrambled and scrambled data . the scrambling operation is enabled by default , but it can be disabled using the spi. for scrambled data , any 0xfc character at the end of a frame is replaced by an /f/ , and any 0x7c character at the end of a multiframe is replaced with an /a/. the jesd204b receiver ( rx ) check s for /f/ and /a/ characters in the received data stream and verifies that they only occur in the expected locations. if an unexpected /f/ or /a/ character is fo und, the receiver handle s the situation by using dynamic realignment or a sserting the syncinb signal for more than four frames to initiate a resynchronization. for un scrambled data, if the final character of two subsequent frames is equal, the second char acter is replaced with an /f/ if it is at the end of a frame, and an /a/ if it is at the end of a multiframe . insertion of alignment characters can be modified using spi. the frame alignment character insertion (faci) is enabled by default. more informat ion on the link controls is available in the memory map section, r egister 0x 571. 8 b/10b encoder the 8 b /10 b e ncoder converts 8 - bit octets int o 10 - bit symbols and inserts control characters into the stream when needed. the control characters used in jesd204b are shown in table 11. the 8 b /10 b encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols . the 8 b /10 b interface has options that can be controlled via the spi. these operatio ns include bypass and invert . th ese options are intended to be troubleshooting tool s for t he verification of the digital front end (dfe). refer to the memory map section , r egister 0x 572 [2:1 ] for information on configuring the 8 b /10 b encoder. table 11. ad9234 control characters u sed in jesd204b abbreviation control symbol 8 - bit v alue 10 - bit valu e , rd 1 = ?1 10 - bit v alue , rd 1 = +1 description / r / / k28.0 / 000 11100 001111 0100 110000 1011 start of multi frame / a / / k28.3 / 011 11100 001111 0011 110000 1100 lane alignment / q / / k28.4 / 100 11100 001111 0010 110000 1101 start of link configuration data / k / / k28.5 / 101 11100 001111 1010 110000 0101 group synchronization / f / / k28.7 / 111 11100 001111 1000 110000 0111 frame alignment 1 rd means running disparity. rev. a | page 40 of 66
data sheet ad9234 physical layer (driv er) outputs digital outputs, timing , and controls the ad9234 physical layer consists of drivers that are defined in the jedec standard jesd204b, j uly 2011 . the differen tial digital outputs are powered up by default. the drivers use a dynamic 100 internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver , which result s in a nominal 300 mv p - p swing at the receiver (see figure 94 ). it is recommended to use ac coupling to connect the ad9234 serdes outputs to the receiver . figure 94 . ac - coupled digital output termination example if there is no far - end receiver termination, or if there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. figure 95 to figure 100 show example s of the digital output data eye, time interval error (tie) jitter histogra m , and bathtub curve for one ad9234 lane running at 10 gbps and 6 gbps , respectively . the format of the output data is twos complement by default. to change the output data format, see the memory map section (register 0x561 in table 22). de - emphasis de - emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the jesd204b specification. use the de - emphasis feature only when the receiver is unable to recover the clock due to excessive ins ertion loss. under normal conditions , it is disabled to conserve power. a dditionally , enabling and setting too high a de - emphasis value on a short link may cause the receiver eye diagram to fail. u s e the de - emphasis setting with caution because it may incr ease electromagnetic interference ( emi ) . see the memory map section (re gister 0x5c1 to register 0x 5c5 in table 22) for more details. phase - locked loop the pll is used to generate the serializer clock, which will operate at the jesd204b lane rate. the jesd204b lane rate register 0x056e[4:3] must be set to correspond with the lane rate . figure 95 . digital outputs data eye , external 100 ? terminations at 10 gbps figure 96 . digital outputs data eye, external 100 ? terminations at 6 gbps serdoutx+ drvdd serdoutx? output swing = 300mv p-p 100 receiver 100 differential trace pair 0.1f 0.1f 12244-054 400 ?400 ?300 ?200 ?100 0 100 200 300 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 voltage (mv) time (ps) 12244-500 tx eye mask 400 ?400 ?300 ?200 ?100 0 100 200 300 ?150 ?100 ?50 0 50 100 150 voltage (mv) time (ps) 12244-503 tx eye mask rev. a | page 41 of 66
ad9234 data sheet rev. a | page 42 of 66 figure 97. digital outputs histogram, external 100 terminations at 10 gbps figure 98. digital outputs bathtub curve, external 100 terminations at 10 gbps figure 99. digital outputs histogram, external 100 terminations at 6 gbps figure 100. digital outputs bathtub curve, external 100 terminations at 6 gbps 12000 10000 8000 6000 4000 2000 0 ?4?20246 hits time (ps) 12244-501 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?16 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 be r ui 12244-502 8000 6000 4000 2000 7000 4000 3000 1000 0 ?4 ?3 ?2 ?1 0 1 3 2 4 hits time (ps) 12244-504 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?16 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ber ui 12244-505
data sheet ad9234 configuring the jesd 204b link the ad9234 has one jesd204b link. the device offers an easy way to set up the jesd204b link through the quick configuration register (register 0x570 ) . the serial outputs (serdout0 to serdout 3) are considered to be part of one jesd204b link. the basic parameters th at determine the link setup are ? number of lanes per link (l) ? number of converters per link (m) ? number of octets per frame (f) the maximum lane rate allowed by the jesd204b specification is 12.5 gbps. the lane line rate is related to the jesd204b parameters using the following equation: l f n m rate line lane out ? ? ? ? ? ? = 8 10 ' where f out = f adc_clock / decimation ratio. the following steps can be used to configure the output: 1. power down the link. 2. select quick configuration options. 3. configure detailed options . 4. set output lane mapping (optional). 5. set additional driver configuration options (optional). 6. power up the link. if the lane line rate calculated is less than 6.25 gbps, select the lo w line rate option. this is done by programming a value of 0x10 to register 0x56e. table 12 and table 13 show the jesd204b output configura - tions supported for both n ? = 16 and n ? = 8 for a given number of virtual converters. care must be taken to ensure that the serial line rate for a given configuration is within the supported range of 3.125 gbps to 1 2.5 gbps . table 12. jesd204b output configurations for n? = 16 number of virtual converters supported (same value as m) jesd204b quick configuration (0x570) jesd204b serial line rate 1 jesd204b transport layer settings 2 l m f s hd n n ? cs k 3 1 0x01 20 f out 1 1 2 1 0 8 to 16 16 0 to 3 only valid k values that are divisible by 4 are supported 0x40 10 f out 2 1 1 1 1 8 to 16 16 0 to 3 0x41 10 f out 2 1 2 2 0 8 to 16 16 0 to 3 0x80 5 f out 4 1 1 2 1 8 to 16 16 0 to 3 0x81 5 f out 4 1 2 4 0 8 to 16 16 0 to 3 2 0x0a 40 f out 1 2 4 1 0 8 to 16 16 0 to 3 0x49 20 f out 2 2 2 1 0 8 to 16 16 0 to 3 0x88 10 f out 4 2 1 1 1 8 to 16 16 0 to 3 0x89 10 f out 4 2 2 2 0 8 to 16 16 0 to 3 4 0x13 80 f out 1 4 8 1 0 8 to 16 16 0 to 3 0x52 40 f out 2 4 4 1 0 8 to 16 16 0 to 3 0x91 20 f out 4 4 2 1 0 8 to 16 16 0 to 3 1 f out = output sample rate = adc sample rate/ chip decimation ratio . the jesd204b serial lin e rate must be 3.125 gbps and 12.5 gbps; when the serial line rate is 12.5 gbps and 6.25 gbps, the low line rate mode must be disabled (set bit 4 to 0x0 in 0x56e). when the serial line rate is <6.25 gbps and 3 . 125 g bps, the low line rate mode must be enabled (set bit 4 to 0x 1 in 0x 56e) . 2 jesd204b transport layer descriptions are as described in the jesd204b overview section. 3 for f = 1, k = 20, 24, 28, and 32. for f = 2, k = 12, 16, 20, 24, 28, and 32. for f = 4, k = 8, 12, 16, 20, 24, 28, and 32. f or f = 8 and f = 16 , k = 4, 8, 12, 16, 20, 24, 28, and 32. table 13. jesd204b output configurations for n? = 8 number of virtual converters supported (same value as m) jesd204b quick configuration (0x570) serial line rate 1 jesd204b transport layer settings 2 l m f s hd n n ? cs k 3 1 0x00 10 f out 1 1 1 1 0 7 to 8 8 0 to 1 only valid k values which are divisible by 4 are supported 0x01 10 f out 1 1 2 2 0 7 to 8 8 0 to 1 0x40 5 f out 2 1 1 2 0 7 to 8 8 0 to 1 0x41 5 f out 2 1 2 4 0 7 to 8 8 0 to 1 0x42 5 f out 2 1 4 8 0 7 to 8 8 0 to 1 0x80 2.5 f out 4 1 1 4 0 7 to 8 8 0 to 1 0x81 2.5 f out 4 1 2 8 0 7 to 8 8 0 to 1 rev. a | page 43 of 66
ad9234 data sheet rev. a | page 44 of 66 number of virtual converters supported (same value as m) jesd204b quick configuration (0x570) serial line rate 1 jesd204b transport layer settings 2 l m f s hd n n? cs k 3 2 0x09 20 f out 1 2 2 1 0 7 to 8 8 0 to 1 0x48 10 f out 2 2 1 1 0 7 to 8 8 0 to 1 0x49 10 f out 2 2 2 2 0 7 to 8 8 0 to 1 0x88 5 f out 4 2 1 2 0 7 to 8 8 0 to 1 0x89 5 f out 4 2 2 4 0 7 to 8 8 0 to 1 0x8a 5 f out 4 2 4 8 0 7 to 8 8 0 to 1 1 f out = output sample rate = adc sample rate/c hip decimation ratio. the jesd204b serial li ne rate must be 3125 mbps and 12,500 mbp s; when the serial line rate is 12.5 gbps and 6.25 gbps, the low line rate mode must be disabled (set bit 4 to 0x0 in register 0x56e). when the serial line r ate is <6.25 gbps and 3.125 gbps, the low line rate mode must be enabled (set bit 4 to 0x1 in register 0x56e). 2 jesd204b transport layer descriptions are as described in the jesd 204b overview section. 3 for f = 1, k = 20, 24, 28, and 32. for f = 2, k = 12, 16, 20, 24, 28, and 32. for f = 4, k = 8, 12, 16, 20, 24, 28, and 32. fo r f = 8 and f = 16, k = 4, 8, 12, 16, 20, 24, 28, and 32. see the example 1: full bandwidth mode section, the example 2: full bandwidth mode at 500 msps section, and the example 3: adc with ddc option (two adcs plus two ddcs) section for examples describing which jesd204b transport layer settings are valid for a given chip mode. example 1: full bandwidth mode at 1 gsps chip application mode is full bandwidth mode (see figure 101). ? two 12-bit converters at 1000 msps ? full bandwidth application layer mode ? no decimation jesd204b output configuration includes the following: ? two virtual converters required (see table 12) ? output sample rate (f out ) = 1000/1 = 1000 msps jesd204b supported output configurations (see table 12) include ? n? = 16 bits ? n = 12 bits ? l = 4, m = 2, and f = 1, or l = 4, m = 2, and f = 2 (quick configuration = 0x88 or 0x89) ? cs = 0 to 2 ? k = 32 ? output serial line rate = 10 gbps per lane, low line rate mode disabled figure 101. full bandwidth mode example 2: full bandwidth mode at 500 msps chip application mode is full bandwidth mode (see figure 101). ? two 12-bit converters at 500 msps ? full bandwidth application layer mode ? no decimation jesd204b output configuration includes the following: ? two virtual converters required (see table 12) ? output sample rate (f out ) = 500/1 = 500 msps jesd204b supported output configurations (see table 12) include ? n? = 16 bits ? n = 12 bits ? l = 4, m = 2, and f = 1, or l = 2, m = 2, and f = 2 (quick configuration = 0x88 or 0x49) ? cs = 0 to 2 ? k = 32 ? output serial line rate ? 5 gbps per lane for l.m.f = 4.2.1, low line rate mode enabled (0x56e = 0x00) ? 10 gbps per lane for l.m.f = 2.2.2, low line rate mode disabled (0x56e = 0x00) jesd204b transmit interface fast detection fast detection cmos cmos converter 0 converter 1 14-bit at 1gbps real/i 14-bit at 1gbps real/q l jesd204b lanes at up to 12.5gbps 12244-060
data sheet ad9234 example 3 : adc with ddc o ption (two adc s plus two ddc s ) chip application mode is t wo - ddc mode. (see figure 102). ? two 12 - bit converters at 1 msps ? two ddc application layer mode with complex outputs (i/q) ? chip decimation ratio = 2 ? ddc decimation ratio = 2 (see table 22) jesd204b output configuration includes the following : ? virtual converters required = 4 (see table 12) ? output sample rate (f out ) = 1000/2 = 500 msps jesd204b supported output configurations include (see table 12) ? n ? = 16 bits ? n = 12 bits ? l = 4 , m = 4, and f = 2 (quick configuration = 0x 91 ) ? cs = 0 to 1 ? k = 32 ? output serial line rate = 10 gbps per lane (l = 4) ? low line rate mode is disabled (0x56e = 0x00) . example 2 shows the flexibility in the digital and lane configurati ons for the ad9234 . the sample rate is 1 gsps, but the outputs are all combined in either one or two lanes, depending on the i/o speed capability of the receiving device. figure 102 . two - adc plus two - ddc mode ddc 0 i converter 0 q converter 1 real/i ddc 1 i converter 2 q converter 3 real/q i/q crossbar mux adc a sampling at f s real adc b sampling at f s real synchronization control circuits sysref l jesd204b lanes up to 12.5gbps l jesd204b lanes at up to 12.5gbps 12244-061 rev. a | page 45 of 66
ad9234 data sheet multi c hip synchronization the ad9234 has a sysref input that allows the user flexible options for synchronizing the internal blocks. the sysref input is a source synchronous system refe rence signal that enables multi chip synchronization. the input clock divider, ddcs, signal monitor block , and jesd204b link can be synchronized using the sysref input. for the highest level of timing accuracy, sysref must meet setup and hold requirements relative to the clk input. the flowchart in figure 103 describes the in ternal mechanism by which multi chip synchronization can be achieved in the ad9234 . the ad9234 supports several features which aid users in meeting the requirements set out for capturing a sysref signal . the sysref sample event can be d efined as either a synchronous low to high transition , or synchronous high to low transition. additionally, the ad9234 allows the sysref signal to be sampled using either the rising edge or falling edge of the clk input . the ad9234 also has the ability to ignore a programmable number (up to 16) of sysref events. the sysref control options can be selected using register 0x120 and register 0x121. rev. a | page 46 of 66
data sheet ad9234 rev. a | page 47 of 66 figure 103. multichip synchronization yes update setup/hold detector status (0x128) increment sysref ignore counter yes no sysref enabled? (0x120) no clock divider > 1? (0x10b) yes no input clock divider alignment required? yes no no yes align clock divider phase to sysref synchronization mode? (0x1ff) timestamp mode normal mode yes sysref inserted in jesd204b control bits back to start no ddc nco alignment enabled? (0x300) yes no no yes send k28.5 characters normal jesd204b initialization sysref control bits? (0x559, 0x55a, 0x58f) reset sysref ignore counter no start sysref asserted? yes no yes align signal monitor counters yes no no yes no increment sysref counter (0x12a) sysref timestamp delay (0x123) back to start sysref ignore counter expired? (0x121) clock divider auto adjust enabled? (0x10d) ramp test mode enabled? (0x550) sysref resets ramp test mode generator jesd204b lmfc alignment required? align phase of all internal clocks (including lmfc) to sysref send invalid 8b/10b characters (all 0's) sync~ asserted signal monitor alignment enabled? (0x26f) align ddc nco phase accumulator 12244-410
ad9234 data sheet rev. a | page 48 of 66 sysref setup/hold window monitor to assist in ensuring a valid sysref signal capture, the ad9234 has a sysref setup/hold window monitor. this feature allows the system designer to determine the location of the sysref signals relative to the clk signals by reading back the amount of setup/hold margin on the interface through the memory map. figure 104 and figure 105 show the setup and hold status values for different phases of sysref. the setup detector returns the status of the sysrefsignal before the clk edge and the hold detector returns the status of the sysref signal after the clk edge. register 0x128 stores the status of sysref and lets the user know if the sysref signal is successfully captured by the adc. figure 104. sysref setup detector figure 105. sysref hold detector valid ? 1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 7 6 5 4 3 2 1 0 reg 0x128[3:0] clk input sysref input flip-flop hold (min) flip-flop hold (min) flip-flop setup (min) 12244-411 clk input sysref input valid reg 0x128[7:4] ? 1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 7 6 5 4 3 2 1 0 flip-flop hold (min) flip-flop hold (min) flip-flop setup (min) 12244-412
data sheet ad9234 table 14 shows the description of the contents of r egister 0x128 and how to interpret them. table 14. sysref setup/hold monitor , register 0x128 register 0 x 128 [ 7:4 ] hold status register 0 x 128 [ 3:0 ] setup status description 0x0 0x0 to 0x7 possible setup error . the smaller this number, the smaller the setup margin . 0x0 to 0x8 0x8 no setup or hold error (best hold margin) . 0x8 0x9 to 0xf no setup or hold error (best setup and hold margin) . 0x8 0x0 no setup or hold error (best setup margin) . 0x9 to 0xf 0x0 possible hold error . the larger this number, the smaller the hold margin. 0x0 0x0 possible setup or hold error . rev. a | page 49 of 66
ad9234 data sheet test modes adc test modes the ad9234 has various test options that aid in the system level implementation. the ad9234 has adc test modes that are available in register 0x550. these test modes are described in table 15. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks, and the test pattern is run through the output formatti ng block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x550. these tests can be performed with or without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. for more information, see the an - 877 application note, interfacing to high speed adcs via spi . table 15. adc test modes 1 output test mode bit sequence pattern name expression default/ seed value sample (n, n + 1, n + 2,.) 0000 off (default) n/a n/a n/ a 0001 midscale short 0000 0000 0000 n/a n / a 0010 +full - scale short 0111 1111 1111 n/a n / a 0011 ? full - scale short 1000 0000 0000 n/a n / a 0100 checkerboard 1010 1010 1010 n/a 0x 0aaa , 0x 0555 , 0x 0aaa , 0x 0555 , 0x 0aaa 0101 pn sequence long x 23 + x 18 + 1 0x3aff 0x3fd7, 0x0002, 0x26e0, 0x0a3d, 0x1ca6 0110 pn sequence short x 9 + x 5 + 1 0x0092 0x125b, 0x3c9a, 0x2660, 0x0c65, 0x0697 0111 one - /zero - word toggle 1111 1111 1111 n/a 0x 0fff, 0x0000, 0x0 fff, 0x0000 , 0x0fff 1000 user input register 0x551 to register 0x558 n/a user pat 1[15:2], user pat 2[15:2], user pat 3[15:2], user pat 4[15:2], user pat 1[15:2] for repeat mode user pat 1[15:2], user pat 2[15:2], user pat 3[15:2], user pat 4[15:2], 0x0000 for single mode 1111 ramp o utput (x) % 2 1 2 n/a (x) % 2 1 2 , (x +1) % 2 1 2 , (x +2) % 2 1 2 , (x +3) % 2 1 2 1 n/a means not applicable. rev. a | page 50 of 66
data sheet ad9234 jesd204b block test modes in addition to the a dc pipeline test modes , the ad9234 also has flexible test modes in the jesd204b block. these test modes are listed in register 0x573 and register 0x574. these test patterns can be injected at various points along the output data path. these test injection points are shown in figure 91. table 16 describes the various test modes available in the jesd204b block. for the ad9234 , a transition from test modes (register 0x573 0x00) to normal mode (register 0x573 = 0x00) requires an spi soft reset. this is done by writing 0x81 to register 0x00 (self cleared). transport layer sample test mode the transport layer samples are implemented in the ad9234 as defined by section 5.1.6.3 in the jedec jesd204b specification . these tests are shown in register 0x571[5]. the test pattern is equival ent to the raw samples from the adc. interface test modes the interface test modes are described in register 0x573 bits[3:0]. these test modes are also explained in table 16 . the interface tests can be injected at various points along the data. see figure 91 for more information on the test injection points. register 0x573 bits[5:4] show where these tests are injected. table 17, table 18 , and table 19 show examples of some of the test modes when injected at the jesd sample input, phy 10 - bit input, and scrambler 8 - bit input. up in the tables represent the user pattern co ntrol bits from the customer register map. table 16. jesd204b interface test modes output test mode bit sequence pattern name expression default 0000 off (default) n ot applicable n ot applicable 0001 alternating checker board 0x5555, 0xaaaa, 0x5555 n ot applicable 0010 1/0 word toggle 0x0000, 0xffff, 0x0000 n ot applicable 0011 31 - bit pn sequence x 31 + x 28 + 1 0x0003afff 0100 23 - bit pn sequence x 23 + x 18 + 1 0x003aff 0101 15 - bit pn sequence x 15 + x 14 + 1 0x03af 0110 9 - bit pn sequence x 9 + x 5 + 1 0x092 0111 7 - bit pn sequence x 7 + x 6 + 1 0x07 1000 ramp output (x) % 2 16 ramp size depends on test injection point 1110 continuous/repeat user test register 0x 551 to register 0x558 u ser pat 1 to user pat 4, then repeat 1111 single user test register 0x 55 1 to register 0x558 u ser pat 1 to user pat 4, then zeroes table 17. jesd204b sample input for m = 2, s = 2, n' = 16 (register 0x573[5:4] = 'b00) frame number converter number sample number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0 0 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 0 1 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 1 0 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 1 1 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 1 0 0 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 0 1 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 1 0 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 1 1 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 2 0 0 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 0 1 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 1 0 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 1 1 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 3 0 0 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 0 1 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 1 0 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 1 1 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 4 0 0 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 0 1 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 1 0 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 1 1 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 rev. a | page 51 of 66
ad9234 data sheet table 18. physical layer 10 - bit input (register 0x573[5:4] = 'b01) 10 - b it symbol number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0x155 0x000 (x) % 2 10 0x125 0x3fd up1[15:6] up1[15:6] 1 0x2aa 0x3ff (x + 1)% 2 10 0x2fc 0x1c0 up2[15:6] up2[15:6] 2 0x155 0x000 (x + 2)% 2 10 0x26a 0x00a up3[15:6] up3[15:6] 3 0x2aa 0x3ff (x + 3)% 2 10 0x198 0x1b8 up4[15:6] up4[15:6] 4 0x155 0x000 (x + 4)% 2 10 0x031 0x028 up1[15:6] 0x000 5 0x2aa 0x3ff (x + 5)% 2 10 0x251 0x3d7 up2[15:6] 0x000 6 0x155 0x000 (x + 6)% 2 10 0x297 0x0a6 up3[15:6] 0x000 7 0x2aa 0x3ff (x + 7)% 2 10 0x3d1 0x326 up4[15:6] 0x000 8 0x155 0x000 (x + 8)% 2 10 0x18e 0x10f up1[15:6] 0x000 9 0x2aa 0x3ff (x + 9)% 2 10 0x2cb 0x3fd up2[15:6] 0x000 10 0x155 0x000 (x + 10)% 2 10 0x0f1 0x31e up3[15:6] 0x000 11 0x2aa 0x3ff (x + 11)% 2 10 0x3dd 0x008 up4[15:6] 0x000 table 19. scrambler 8 - bit input (register 0x573[5:4] = 'b10) 8 - bit octet number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0x55 0x00 (x) % 2 8 0x49 0xff up1[15:9] up1[15:9] 1 0xaa 0xff (x + 1)% 2 8 0x6f 0x5c up2[15:9] up2[15:9] 2 0x55 0x00 (x + 2)% 2 8 0xc9 0x00 up3[15:9] up3[15:9] 3 0xaa 0xff (x + 3)% 2 8 0xa9 0x29 up4[15:9] up4[15:9] 4 0x55 0x00 (x + 4)% 2 8 0x98 0xb8 up1[15:9] 0x00 5 0xaa 0xff (x + 5)% 2 8 0x0c 0x0a up2[15:9] 0x00 6 0x55 0x00 (x + 6)% 2 8 0x65 0x3d up3[15:9] 0x00 7 0xaa 0xff (x + 7)% 2 8 0x1a 0x72 up4[15:9] 0x00 8 0x55 0x00 (x + 8)% 2 8 0x5f 0x9b up1[15:9] 0x00 9 0xaa 0xff (x + 9)% 2 8 0xd1 0x26 up2[15:9] 0x00 10 0x55 0x00 (x + 10)% 2 8 0x63 0x43 up3[15:9] 0x00 11 0xaa 0xff (x + 11)% 2 8 0xac 0xff up4[15:9] 0x00 data link layer test modes the data link layer test modes are implemented in the ad9234 as defined by section 5.3.3.8.2 in the jedec jesd204b specification. these tests are shown in register 0x574 bits[2:0]. test patterns inserted at this point are useful for verifying the functionality of the data link layer. when the data link layer test modes are enabled, disab le syncinb by writing 0xc0 to register 0x572. rev. a | page 52 of 66
data sheet ad9234 serial port interfac e the ad9234 spi allows the user to configure the converter for speci fic functions or operations thro ugh a structured register space provided inside the adc. the spi gives the user added flexibility and c ustomization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information , see the serial control interfac e standard (rev. 1.0) . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 20 ). the sclk (seria l clock) pin synchronize s the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc me mory map registers. the csb (chip select bar) pin is an a ctive low control that enables or disables the read and write cycles. table 20 . serial port interface pins pin function sclk serial clock . the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar . an active low control that gates the read and write cycles. the falling edge of csb , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 3 and table 5 . other modes involving the csb pin are available. the csb pin can be held low indefinitely, which permanently enables the device; this is called streaming. the csb pin can stall high between bytes to allow additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the sdio pin to change direction from an input to an outp ut. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a re ad - back operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the serial control interface standard (rev. 1.0) . hardware in terface the pins described in table 20 comprise the physical interface between the user programming device and the serial port of the ad9234 . the sc lk pin and the csb pin function as inputs when using the spi. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , microcontroller - based seri al port interface (spi) boot circuit . do not activate t he spi port during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noi se from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9234 to prevent these signals from transition - ing at the converter inputs during critical sampling periods. spi accessible featu res table 21 provides a brief description of the general fea tures that are accessible via the spi. these features are described in detail in the serial control interface standard (rev. 1.0) . the ad9234 device specif ic features are described in the memory map section . table 21 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode . clock allows the user to access the clock divider via the spi . ddc allows the user to set up decimation filters for different applications. test i nput /o utput allows the user to set test modes to have known data on output bits . output mode allows the user to set up outputs . serdes output setup allows the user to v ary serdes settings such as swing and emphasis . rev. a | page 53 of 66
ad9234 data sheet memory map reading the memory m ap register table each row in the memory map register table has eight bit locations. the memory map is divided into four sections: the analog devices spi regist ers (register 0x000 to register 0x00d ), the adc function regist ers (register 0x015 to register 0x27a ), the ddc function registers (register 0x300 to register 0x 347) , and the digital outputs and test modes regist ers (register 0x550 to register 0x5c5). table 22 (see the memory map section ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x 561 , the output mode register, has a hexadecimal default value of 0x0 1 . this means tha t bit 0 = 1, and the remaining bits are 0s. this setting is the default output format value, which is twos comple - ment. for more information on this function and others, see the table 22. open and reserved locations all address and bit locations that are not included in table 22 are not currently supported for this devic e. write u nused bits of a valid address location with 0s unless the default value is set otherwise . writing to these locations is required only when part of an address location is unassigned (for example, address 0x 561) . if the entire address location i s open (for example, address 0x 0 13), do not write to this address location. default values after the ad9234 is reset, critical registers are loaded with default values. the default values for the registers a re given in table 22. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. ? x denotes a d o n t care bit. channel - specific registers some channel setup functions , such as the input termination ( register 0x 016), can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 22 as local. these local registers and bits can be accessed by setting the appropriate channel a o r channel b bits in register 0x 008. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, set only channel a or channel b to read one of the two registers. if both bits are set during an spi read cycle, the device returns the value for channel a. registers and bits designated as global in table 22 affect the entire device and the channel features for which independent settings are not allowed between channels. the settings in register 0x 0 05 do not affect the global registers and bits. spi soft reset after issuing a soft reset by pr ogramming 0x81 to r egister 0x00 0, the ad9234 requires 5 ms to recover. w hen programming the ad9234 fo r application setup, ensure that an adequate delay is programmed in to the firmware af ter asserting the soft reset and before starting the device setup. rev. a | page 54 of 66
data sheet ad9234 memory map register table all address locations that are not included in table 22 are not currently supported for this device and must not be written . table 22 . memory map registers reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes analog devices spi registers 0x000 interface_ config_a soft reset (self clearing) lsb f irst 0 = msb 1 = lsb address as cension 0 0 address ascension lsb f irst 0 = msb 1 = lsb soft reset (self clearing) 0x00 0x001 interface_ config_b single instruction 0 0 0 0 0 datapath soft reset (self clearing) 0 0x00 0x002 device_ config (local) 0 0 0 0 0 0 00 = normal operation 10 = standby 11 = power - down 0x00 0x003 chip_type 0 0 0 0 011 = high speed adc 0x03 read only 0x004 chip_id (low byte) 1 1 0 0 1 1 1 0 0xc e read only 0x005 chip_id (high byte) 0 0 0 0 0 0 0 0 0x00 read only 0x006 chip_grade 1010 = 1000 msps 0101 = 500 msps x x x x 0xax for ad9234 - 1000 0x5x for ad9234 - 500 read only 0x008 device index 0 0 0 0 0 0 channel b ch annel a 0x03 0x00a scratch pad 0 0 0 0 0 0 0 0 0x00 0x00b spi revision 0 0 0 0 0 0 0 1 0x01 0x00c vendor id (low byte) 0 1 0 1 0 1 1 0 0x56 read only 0x00d vendor id (high byte) 0 0 0 0 0 1 0 0 0x04 read only adc function registers 0x015 analog input (local) 0 0 0 0 0 0 0 input disable 0 = norm al operation 1 = input disabled 0x00 0x016 input termination (local) analog input differential termination 0000 = 400 0001 = 200 0010 = 100 0110 = 50 0011 = ad9234 - 1000 0001 = ad9234 - 500 0x03 for ad9234 - 1000 ; 0x 01 for ad9234 - 500 0x018 input buffer current control (local) 0000 = 1.0 buffer current 0001 = 1.5 buffer current 0010 = 2.0 buffer current 0011 = 2.5 buffer current 0100 = 3.0 buffer current 0101 = 3.5 buffer current 1111 = 8.5 buffer current 0 0 0 0 0x 30 for ad9234 - 1000 ; 0x 20 for ad9234 - 500 0x024 v_1p0 control 0 0 0 0 0 0 0 1.0 v refer - ence select 0 = internal 1 = external 0x00 rev. a | page 55 of 66
ad9234 data sheet reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x028 temp erature diode (local) 0 0 0 0 0 0 0 diode selection 0 = no diode selected 1 = temper ature diode selected 0x00 used in con junc - tion with reg . 0x040 0x03f pdwn/ stby pin control (local) 0 = pdwn/ stby enabled 1 = disabled 0 0 0 0 0 0 0 0x00 used in con junc - tion with reg . 0x040 0x040 chip pin control pdwn/stby function 00 = power down 01 = standby 10 = disabled fast d etect b (fd_b) 000 = fast detect b output 001 = jesd204b lmfc output 010 = jesd204b internal sync~ output 111 = d isabled fast detect a (fd_a) 000 = fast detect a output 001 = jesd204b lmfc output 010 = jesd204b internal sync~ output 011 = temperature diode 111 = d isabled 0x3f 0x10b clock divider 0 0 0 0 0 000 = divide by 1 001 = divide by 2 011 = divide by 4 111 = divide by 8 0x00 0x10c clock divider phase (local) 0 0 0 0 independently controls channel a and channel b clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ? input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1? input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2? input clock cycles delayed 1111 = 7? input clock cycles delayed 0x00 0x10d clock divider and sysref control clock divider auto phase adjust 0 = disabled 1 = enabled 0 0 0 clock divider negative skew window 00 = no negative skew 01 = 1 device clock of negative skew 10 = 2 device clocks of negative skew 11 = 3 device clocks of negative skew clock divider positive skew window 00 = no positive skew 01 = 1 device clock of positive skew 10 = 2 device clock s of positive skew 11 = 3 device clocks of positive skew 0x00 clock divider must be >1 0x117 clock delay control 0 0 0 0 0 0 0 clock fine delay adjust enable 0 = disabled 1 = enabled 0x00 enabling the clock fine delay adjust causes a datapath reset 0x118 clock fine delay (local) clock fine delay adjust[7:0] , twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ?88 = ? 151.7 ps skew ?87 = ? 15 0 ps skew 0 = 0 ps skew +87 = +150 ps skew 0x00 used in con - junction with reg . 0x0117 0x11c clock status 0 0 0 0 0 0 0 0 = no input clock detected 1 = input clock det - ected read only rev. a | page 56 of 66
data sheet ad9234 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x120 sysref control 1 0 sysref flag reset 0 = normal operat ion 1 = flags held in reset 0 sysref transition select 0 = low to high 1 = high to low clk edge select 0 = rising 1 = falling sysref mode select 00 = disabled 01 = continuous 10 = n shot 0 0x00 0x121 sysref control 2 0 0 0 0 sysref n - shot ignore counter select 0000 = next sysref only 0001 = ignore the first sysref transitions 0010 = ignore the first two sysref transitions 1111 = ignore the first 16 sysref transitions 0x00 mode select , reg . 0x120 , bit s [2:1], must be n shot 0x123 sysref timestamp delay control 0 sysref timestamp delay , bits [6:0] 0x00 = no delay 0x01 = 1 clock delay 0x7f = 127 clocks delay 0x00 ignored when reg . 0x01ff = 0x00 0x128 sysref status 1 sysref hold status, register 0x128[7:4] , r efer to table 14 sysref setu p status, register 0x128 [3:0] , r efer to table 14 read only 0x129 sysref and clock divider status 0 0 0 0 clock divider phase when sysref was captured 0000 = in - phase 0001 = sysref is ? cycle delayed from clock 0010 = sysref is 1 cycle delayed from clock 0011 = 1? input clock cycles delayed 0100 = 2 input clock cycle s delayed 0101 = 2? input clock cycles delayed 1111 = 7? input clock cycles delayed read only 0x12a sysref counter sysref counter, bits[7:0] increments when a sysref signal is captured read only 0x1ff chip sync mode 0 0 0 0 0 0 synchronization mode 00 = normal 01 = timestamp 0x00 0x200 chip application mode 0 0 chip q ignore 0 = normal (i/q) 1 = ignore (iC only) 0 0 0 chip operating mode 00 = full bandwidth mode 01 = ddc 0 on 10 = ddc 0 and ddc 1 0x00 0x201 chip decimation ratio 0 0 0 0 0 chip decimation ratio select 000 = full sample rate (decimate = 1) 001 = decimate by 2 0x00 0x228 customer offset offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 0x245 fast detect (fd) control (local) 0 0 0 0 force fd_a / fd_b pins; 0 = normal func tion; 1 = force to value force value of fd_a/ fd_b pins if force pins is true, this value is output on fd pins 0 enable fast detect output 0x00 0x247 fd upper threshold lsb (l ocal) fast detect upper threshold, bits[7:0] 0x00 0x248 fd upper threshold msb (l ocal) 0 0 0 fast detect upper threshold, bits[12:8] 0x00 rev. a | page 57 of 66
ad9234 data sheet reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x249 fd lower threshold lsb ( local) fast detect lower threshold, bits[7:0] 0x00 0x24a fd lower threshold msb ( local) 0 0 0 fast detect lower threshold, bits[12:8] 0x00 0x24b fd dwell time lsb ( local) fast detect dwell time, bits[7:0] 0x00 0x24c fd dwell time msb ( local) fast detect dwell time, bits[15:8] 0x00 0x26f signal , onitor s ynchro nizatio n c ontrol 0 0 0 0 0 0 synchronization m ode 00 = disabled 01 = c ontinuous 1 1 = one shot 0x00 refer to the signal monitor section 0x270 signal monitor control (local) 0 0 0 0 0 0 peak d etector 0 = d isabled 1 = e nabled 0 0x00 0x271 signal monitor period register 0 ( local) signal monitor period , bits [7:0] 0x80 in decimated output clock cycles 0x272 signal monitor period register 1 ( local) signal monitor period , bits [15:8] 0x00 in decimated output clock cycles 0x273 signal monitor period register 2 ( local) signal monitor period , bits [23:16] 0x00 in decimated output clock cycles 0x274 signal monitor result control (local) 0 0 0 result u pdate 1 = u pdate results ( s elf clear) 0 0 0 result selection 0 = r eserved 1 = p eak detector 0x01 0x275 signal monitor result register 0 ( local) signal monitor result, bits [7:0] when register 0x0274[0] = 1, result bits [19: 7 ] = peak detector absolute value [1 2 :0] ; result bits [6:0] = 0 read only updated based on reg . 0x 274[4] 0x276 signal monitor result register 1 ( local) signal monitor result , bits [15:8] read only updated based on reg . 0x 274[4] 0x277 signal monitor result register 1 ( local) 0 0 0 0 signal monitor result, bits [19:16] read only updated based on reg . 0x 274[4] 0x278 signal monitor period counter result ( local ) period count result, bits [7:0] read only updated base d on reg . 0x 274[4] 0x279 signal monitor sport over jesd 204b control ( local ) 0 0 0 0 0 0 00 = reserved 11 = enable 0x00 0x27a sport over jesd 204b input selection ( local) 0 0 0 0 0 0 peak detector 0 = disabled 1 = enabled 0 0x00 rev. a | page 58 of 66
data sheet ad9234 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes ddc function registers (see the digital downconverter (ddc) section) 0x300 ddc synch control 0 0 0 ddc nco soft reset 0 = normal operation 1 = reset 0 0 synchronization mode (triggered by sysref ) 00 = disabled 01 = continuous 1 1 = 1 - shot 0x310 ddc 0 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if (intermediate frequency) mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode (mixer bypassed, nco disabled) 10 = f adc /4 hz if mode (f adc /4 down mixing mode) 11 = test mode (mixer inputs forced to +fs, nco enabled) complex to real enable 0 = disabled 1 = e nabled 0 decimation rate select (complex to real disabl ed) 11 = decimate by 2 (complex to real enabled) 11 = decimate by 1 0x00 0x311 ddc 0 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x00 0x314 ddc 0 frequency lsb ddc 0 nco frequency value, bits[7:0] , twos complement 0x00 0x315 ddc0 frequency msb x x x x ddc 0 nco frequency value, bits[11:8] , twos complement 0x00 0x 320 ddc 0 phase lsb ddc 0 nco phase value, bits[7:0] , twos complement 0x00 0x321 ddc 0 phase msb x x x x ddc 0 nco phase value, bits[11:8] , twos complement 0x00 0x327 ddc 0 output test mode selection 0 0 0 0 0 q output test mode enable 0 = disabled 1 = enabled from ch b 0 i output test mode enable 0 = disabled 1 = enabled from ch a 0x00 0x330 ddc 1 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if (intermediate frequency) mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode (mixer bypassed, nco disabled) 10 = f adc /4 hz if mode (f adc /4 downmixing mode) 11 = test mode (mixer inputs forced to +fs, nco enabled) complex to real enable 0 = disabled 1 = enabled 0 decimation rate select (complex to real disabl ed) 11 = decimate by 2 (complex to real enabled) 11 = decimate by 1 0x00 0x331 ddc 1 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x00 0x334 ddc 1 frequency lsb ddc 1 nco frequency value, bits[7:0] , twos complement 0x00 0x335 ddc 1 frequency msb x x x x ddc 1 nco frequency value, bits[11:8] , twos complement 0x00 0x340 ddc 1 phase lsb ddc 1 nco phase value, bits[7:0] , twos complement 0x00 0x341 ddc 1 phase msb x x x x ddc 1 nco phase value, bits[11:8] , twos complement 0x00 rev. a | page 59 of 66
ad9234 data sheet reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x347 ddc 1 output test mode selection 0 0 0 0 0 q output test mode enabl e 0 = disabled 1 = enabled from ch b 0 i output test mode enable 0 = disabled 1 = enabled from ch a 0x00 digital outputs and test modes 0x550 adc test modes (local) user pattern selection 0 = contin - uous repeat 1 = single pattern 0 reset pn long gen 0 = long pn enable 1 = long pn reset reset pn short gen 0 = short pn enable 1 = short pn reset test mode selection 0000 = off, normal operation 0001 = mids cale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = pn sequence, long 0110 = pn sequence, short 0111 = 1/0 word toggle 1000 = the user pattern te st mode (used with register 0x 550, bit 7 and user pattern ( 1, 2, 3, 4 ) registers) , 1111 = ramp output 0x00 0x551 user pattern 1 lsb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x552 user pattern 1 msb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x553 user pattern 2 lsb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x554 user pattern 2 msb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x555 user pattern 3 lsb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x556 user pattern 3 msb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x557 user pattern 4 lsb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x558 user pattern 4 msb 0 0 0 0 0 0 0 0 0x00 used with reg . 0x550 and reg . 0x573 0x559 output mode control 1 0 converter control bit 1 selection 000 = tie low (1b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (fd) bit 101 = sysre f only used when cs (register 0x58f) = 2 or 3 0 converter control bit 0 selection 000 = tie low (1b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (fd) bit 101 = sysref only used when cs (register 0x58f) = 3 0x00 rev. a | page 60 of 66
data sheet ad9234 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x55a output mode control 2 0 0 0 0 0 converter control bit 2 selection 000 = tie low (1b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (fd) bit 101 = sysref used when cs (register 0x58f) = 1, 2, or 3 0x01 0x561 output mode 0 0 0 0 0 sample invert 0 = normal 1 = sample invert data format select 00 = offset binary 01 = twos complement 0x01 0x562 output overrange (or) clear virtual converter 7 or 0 = or bit enabled 1 = or bit cleared virtual con vert er 6 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 5 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 4 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 3 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 2 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 1 or 0 = or bit enabled 1 = or bit cleared virtual con - verter 0 or 0 = or bit enabled 1 = or bit cleared 0x00 0x563 output or status virtual con - verter 7 or 0 = no or 1 = or occured virtual con - vert er 6 or 0 = no or 1 = or occured virtual con - verter 5 or 0 = no or 1 = or occured virtual converter 4 or 0 = no or 1 = or occured virtual converter 3 or 0 = no or 1 = or occured virtual con - verter 2 or 0 = no or 1 = or occured virtual con - verter 1 or 0 = no or 1 = or occured virtual con - verter 0 or 0 = no or 1 = or occured 0x00 read only 0x564 output channel select 0 0 0 0 0 0 0 converter channel swap 0 = normal channel ordering 1 = channel swap enabled 0x00 0x56e jesd204b lane rate control 0 0 0 0 = serial lane rate 6.25 gbps and 12.5 gbps 1 = serial lane rate must be 3.125 gbps and 6.25 gbps 0 0 0 0 0x00 for ad9234 - 1000 ; 0x10 for ad9234 - 500 0x570 jesd204b quick config - uration jesd204b quick configuration l = number of lanes = 2 register 0x570, bits[7:6] m = number of converters = 2 register 0x570, bits[5:3] f = number of octets/frame = 2 register 0x570, bits[2:0] 0x88 refer to table 12 and table 13 0x571 jesd204b link mode control 1 standby mode 0 = all converter outpu ts 0 1 = cgs (/k28.5/) tail bit (t) pn 0 = disable 1 = enable t = n ? ? n ? cs long transport layer test 0 = disable 1 = enable lane synchron - ization 0 = disable faci uses /k28.7/ 1 = enable faci uses /k28.3/ and /k28.7/ ilas sequence mode 00 = ilas disa bled 01 = ilas enabled 11 = ilas always on test mode faci 0 = enabled 1 = disabled link control 0 = active 1 = power down 0x14 rev. a | page 61 of 66
ad9234 data sheet reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x572 jesd204b link mode control 2 syncinb pin control 00 = normal 10 = ignore syncinb (force cgs) 11 = ignore syncinb (force ilas/user data) sync - inb pin invert 0 = active low 1 = active high syncinb pin type 0 = differential 1 = cmos 0 8b/10b bypass 0 = normal 1 = bypass 8b/10b bit invert 0 = normal 1 = invert the a j symbols 0 0x00 0x573 jesd204b link mode control 3 chksum mode 00 = sum of all 8 - bit link config registers 01 = sum of individual link config fields 10 = checksum set to zero test injection point 00 = n? sample input 01 = 10 - bit data at 8b/10b output (for phy testing) 10 = 8 - bit data at scrambler input jesd204b test mode patterns 0000 = normal operation (test mode disabled) 0001 = alternating checker board 0010 = 1/0 word toggle 0011 = 31 - bit pn sequence x 31 + x 28 + 1 0100 = 23 - bit pn sequence x 23 + x 18 + 1 0101 = 15 - bit pn sequence x 15 + x 14 + 1 0110 = 9 - bit pn sequence x 9 + x 5 + 1 0111 = 7 - bit pn sequence x 7 + x 6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test 0x00 0x574 jesd204b link mode control 4 ilas delay 0000 = transmit ilas on first lmfc after syncinb deasserted 0001 = transmit ilas on second lmfc after syncinb deasserted 1111 = transmit ilas on 16 th lmfc after syncinb deasserted 0 link layer test mode 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /d21.5/ charac ters 100 = modified rpat test sequence 101 = jspat test sequence 110 = jtspat test sequence 0x00 0x578 jesd204b lmfc offset 0 0 0 lmfc phase offset value , bits [4:0] 0x00 0x580 jesd204b did config jesd204b tx did value , bits [7:0] 0x00 0x581 jesd204b bid config 0 0 0 0 jesd204b tx bid value, bits[7:0] 0x00 0x583 jesd204b lid config 1 0 0 0 lane 0 lid value, bits[4:0] 0x00 0x584 jesd204b lid config 2 0 0 0 lane 1 lid value, bits[4:0] 0x01 0x585 jesd204b lid config 3 0 0 0 lane 2 lid value, bits[4:0] 0x01 0x586 jesd204b lid config 4 0 0 0 lane 3 lid value, bits[4:0] 0x03 0x58b jesd204b parameters scr/l jesd204b scrambling (scr) 0 = disabled 1 = enabled 0 0 0 0 0 jesd204b lanes (l) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes read only, see register 0x570 0x8x 0x58c jesd204b f config number of octets per frame, f = register 0x58c , bits [7:0] + 1 0x88 read only, see reg. 0x570 0x58d jesd204b k config 0 0 0 number of frames per multiframe, k = register 0x58d, bits[4:0] + 1 only values where (f k) mod 4 = 0 are supported 0x1f see reg. 0x570 0x58e jesd204b m config number of converters per link , bits [7:0] 0x00 = link connected to one virtual converter (m = 1) 0x01 = link connected to two virtual converters (m = 2) 0x03 = link connected to four virtual converters (m = 4) 0x07 = link connected to eight virtual converters (m = 8) read only rev. a | page 62 of 66
data sheet ad9234 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x58f jesd204b cs/n config number of control bits (cs) per sample 00 = no control bits (cs = 0) 01 = 1 control bit (cs = 1); control bit 2 only 10 = 2 control bits (cs = 2); control bit 2 and control bit 1 only 11 = 3 control bits (cs = 3); all control bits (2, 1, 0) 0 adc converter resolution (n) 0x06 = 7 - bit resolution 0x07 = 8 - bit resolution 0x08 = 9 - bit resolution 0x09 = 10 - bit resolution 0x0a = 11 - b it resolution 0x0b = 12 - bit resolution 0x0c = 13 - bit resolution 0x0d = 14 - bit resolution 0x0e = 15 - bit resolution 0x0f = 16 - bit resolution 0x0f 0 x0590 jesd204b n config subclass support (subclass version) 000 = subclass 0 (no deterministic latency) 001 = subclass 1 adc number of bits per sample (n) 0x7 = 8 bits 0xf = 16 bits 0x2f 0x591 jesd204b s config 0 0 1 samples per converter frame cycle (s) s value = register 0x591[4:0] +1 read only 0x592 jesd204b hd and cf config uration hd value 0 = disabled 1 = enabled 0 0 control words per frame clock cycle per link (cf) cf value = register 0x592, bits[4:0] 0x80 read only 0x5a0 jesd204b chksum 0 chksum value for serdout0, bits[7:0] 0x81 read only 0x5a1 jesd204b chksum 1 chksum value for serdout1, bits[7:0] 0x82 read only 0x5a2 jesd204b chksum 2 chksum value for serdout2, bits[7:0] 0x82 read only 0x5a3 jesd204b chksum 3 chksum value for serdout3, bits[7:0] 0x84 read only 0x5b0 jesd204b lane power - down 1 serd - out3 0 = on 1 = off 1 serd - out2 0 = on 1 = off 1 serd - out1 0 = on 1 = off 1 serd out0 0 = on 1 = off 0xaa 0x5b2 jesd 204b lane serd out0 assign x x x x 0 serdout0 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x00 0x5b3 jesd204b lane serd out1 assign x x x x 0 serdout1 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x11 0x5b5 jesd204b lane serd out2 assign x x x x 0 serdout2 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x22 0x5b6 jesd204b lane serd out3 assign x x x x 0 serdout3 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x33 rev. a | page 63 of 66
ad9234 data sheet reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x5bf jesd serializer drive adjust 0 0 0 0 swing voltage 0000 = 237.5 mv 0001 = 250 mv 0010 = 262.5 mv 0011 = 275 mv 0100 = 287.5 mv 0101 = 300 mv (default) 0110 = 312.5 mv 0111 = 325 mv 1000 = 337.5 mv 1001 = 350 mv 1010 = 362.5 mv 1011 = 375 mv 1100 = 387.5 mv 1101 = 400 mv 1110 = 412.5 mv 1111 = 425 mv 0x05 0x5c1 de - emphasis select 0 serd - out3 0 = disable 1 = enable 0 serd - out2 0 = disable 1 = enable 0 serd - out1 0 = disable 1 = enable 0 serdout0 0 = disable 1 = enable 0x00 0x5c2 de - emphasis setting for serdout0 0 0 0 0 serdout0 d e - emphasis settings: 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c3 de - emphasis setting for serdout1 0 0 0 0 serdout1 d e - emphasis settings: 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c4 de - emphasis setting for serdout2 0 0 0 0 serdout2 d e - emphasis settings: 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c5 de - emphasis setting for serdout3 0 0 0 0 serdout3 d e - emphasis settings: 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 rev. a | page 64 of 66
data sheet ad9234 rev. a | page 65 of 66 applications information power supply recommendations the ad9234 must be powered by the following seven supplies: avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, and spivdd = 1.8 v. for applications requiring an optimal high power efficiency and low noise performance, it is recommended that the adp2164 and adp2370 switching regulators be used to convert the 3.3 v, 5.0 v, or 12 v input rails to an intermediate rail (1.8 v and 3.8 v). these intermediate rails are then postregulated by very low noise, low dropout (ldo) regulators ( adp1741 , adm7172 , and adp125 ). figure 106 shows the recommended power supply scheme for ad9234. figure 106. high efficiency, low noise power solution for the ad9234 it is not necessary to split all of these power domains in all cases. the recommended solution shown in figure 106 provides the lowest noise, highest efficiency power delivery system for the ad9234 . if only one 1.25 v supply is available, route to avdd1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for avdd1_sr, spivdd, dvdd, and drvdd, in that order. the user can employ several different decoupling capacitors to cover both high and low frequencies. these must be located close to the point of entry at the pcb level and close to the devices, with minimal trace lengths. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connected to ground to achieve the best electrical and thermal performance of the ad9234 . connect an exposed continuous copper plane on the pcb to the ad9234 exposed pad, pin 0. the copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias must be solder filled or plugged. the number of vias and the fill determine the resultant ja measured on the board. this is shown in table 7. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 107 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . fig ure 107. recommended pcb layout of exposed pad for the ad9234 avdd1_sr (pin 57) and agnd (pin 56 and pin 60) avdd1_sr (pin 57) and agnd (pin 56 and pin 60) can be used to provide a separate power supply node to the sysref circuits of ad9234 . if running in subclass 1, the ad9234 can support periodic one-shot or gapped signals. to minimize the coupling of this supply into the avdd1 supply node, adequate supply bypassing is needed. avdd1 1.25v avdd1_sr 1.25v dvdd 1.25v spivdd (1.8v or 3.3v) 3.6v 3.3v drvdd 1.25v 1.8v 12244-063 adp1741 adp125 avdd3 3.3v adm7172 or adp1741 avdd2 2.5v adp1741 12244-064
ad9234 data sheet rev. a | page 66 of 66 outline dimensions figure 108. 64-lead lead frame chip scale package [lfcsp_wq] 9 mm 9 mm body, very thin quad (cp-64-15) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9234bcpz-500 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_wq] cp-64-15 ad9234bcpzrl7-500 ?40c to +85c 64-lead lead fr ame chip scale package [lfcsp_wq] cp-64-15 ad9234bcpz-1000 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_wq] cp-64-15 ad9234bcpzrl7-1000 ?40c to +85c 64-lead lead fr ame chip scale package [lfcsp_wq] cp-64-15 ad9234-500ebz evaluation board for ad9234-500 (optimized for full analog input frequency range) AD9234-1000EBZ evaluation board for ad9234-1000 (optimized for full analog input frequency range) 1 z = rohs compliant part. 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r 7.70 7.60 sq 7.50 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-12-2014-a 9.10 9.00 sq 8.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min 7.50 ref compliant to jedec standards mo-220-wmmd 1 64 16 17 49 48 32 33 pkg-004396 ?2014C 2015 analog devices, inc. all righ ts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12244-0-3/15(a)

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